參數(shù)資料
型號: ST7PDALIF2M6
廠商: 意法半導(dǎo)體
元件分類: ADC
英文描述: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI, DALI
中文描述: 8位單電壓閃存存儲器,數(shù)據(jù)EEPROM,模數(shù)轉(zhuǎn)換器,定時器,SPI和大理微控制器
文件頁數(shù): 120/141頁
文件大?。?/td> 2175K
代理商: ST7PDALIF2M6
ST7DALI
120/141
CONTROL PIN CHARACTERISTICS
(Cont’d)
Figure 86. RESET pin
protection when LVD is enabled.
1)2)3)4)5)
Figure 87. RESET pin protection when LVD is disabled.
1)2)3)
1. The reset network protects the device against parasitic resets.
2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
3. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the V
IL
max. level specified in
section 13.9.1 on page 119
. Otherwise the reset will not be taken into account internally.
4. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value
specified for I
INJ(RESET)
in
section 13.2.2 on page 101
.
5. When the LVD is enabled, it is mandatory not to to connect a pull-up resistor and a capacitor to V
DD
on the RESET pin
.
0.01
μ
F
ST72XXX
PULSE
GENERATOR
Filter
R
ON
V
DD
WATCHDOG
LVD RESET
INTERNAL
RESET
RESET
EXTERNAL
Recommended
0.01
μ
F
V
DD
0.01
μ
F
EXTERNAL
RESET
CIRCUIT
USER
V
DD
4.7k
Required
Recommended
ST72XXX
PULSE
GENERATOR
Filter
R
ON
V
DD
WATCHDOG
INTERNAL
RESET
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