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參數(shù)資料
| 型號： | ST7PDALIF2M6 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | ADC |
| 英文描述： | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI, DALI |
| 中文描述： | 8位單電壓閃存存儲器，數(shù)據(jù)EEPROM，模數(shù)轉(zhuǎn)換器，定時器，SPI和大理微控制器 |
| 文件頁數(shù)： | 23/141頁 |
| 文件大?。?/td> | 2175K |
| 代理商： | ST7PDALIF2M6 |
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ST7DALI
23/141
7 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components.
Main features
■
Clock Management
– 1 MHz internal RC oscillator (enabled by op-
tion byte)
– 1 to 16 MHz or 32kHz External crystal/ceramic
resonator (selected by option byte)
– External Clock Input (enabled by option byte)
– PLL for multiplying the frequency by 8 or 4
(enabled by option byte)
– For clock ART counter only: PLL32 for multi-
plying the 8 MHz frequency by 4 (enabled by
option byte). The 8 MHz input frequency is
mandatory and can be obtained in the follow-
ing ways:
–1 MHz RC + PLLx8
–16 MHz external clock (internally divided
by 2)
–2 MHz. external clock (internally divided by
2) + PLLx8
–Crystal oscillator with 16 MHz output fre-
quency (internally divided by 2)
■
Reset Sequence Manager (RSM)
■
System Integrity Management (SI)
– Main supply Low voltage detection (LVD) with
reset generation (enabled by option byte)
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply (en-
abled by option byte)
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT
The device contains an internal RC oscillator with
an accuracy of 1% for a given device, temperature
and voltage range (4.5V-5.5V). It must be calibrat-
ed to obtain the frequency required in the applica-
tion. This is done by software writing a calibration
value in the RCCR (RC Control Register).
Whenever the microcontroller is reset, the RCCR
returns to its default value (FFh), i.e. each time the
device is reset, the calibration value must be load-
ed in the RCCR. Predefined calibration values are
stored in EEPROM for 3 and 5V V
DD
supply volt-
ages at 25°C, as shown in the following table.
Note:
– See “ELECTRICAL CHARACTERISTICS” on
page 100. for more information on the frequency
and accuracy of the RC oscillator.
– To improve clock stability, it is recommended to
place a decoupling capacitor between the V
DD
and V
SS
pins.
– These two bytes are systematically programmed
by ST, including on FASTROM devices. Conse-
quently, customers intending to use FASTROM
service must not use these two bytes.
– RCCR0 and RCCR1 calibration values will be
erased if the read-out protection bit is reset after
it has been set. See “Read out Protection” on
page 14.
Caution:
If the voltage or temperature conditions
change in the application, the frequency may need
to be recalibrated.
Refer to application note AN1324 for information
on how to calibrate the RC frequency using an ex-
ternal reference signal.
7.2 PHASE LOCKED LOOP
The PLL can be used to multiply a 1MHz frequen-
cy from the RC oscillator or the external clock by 4
or 8 to obtain f
OSC
of 4 or 8 MHz. The PLL is ena-
bled and the multiplication factor of 4 or 8 is select-
ed by 2 option bits.
– The x4 PLL is intended for operation with V
DD
in
the 2.4V to 3.3V range
– The x8 PLL is intended for operation with V
DD
in
the 3.3V to 5.5V range
Refer to
Section 15.1
for the option byte descrip-
tion.
If the PLL is disabled and the RC oscillator is ena-
bled, then f
OSC =
1MHz.
If both the RC oscillator and the PLL are disabled,
f
OSC
is driven by the external clock.
RCCR
Conditions
ST7DALI
Address
RCCR0
V
DD
=5V
T
A
=25°C
f
RC
=1MHz
V
DD
=3V
T
A
=25°C
f
RC
=700KHz
1000h
and FFDEh
RCCR1
1001h
and FFDFh
1
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