參數(shù)資料
型號(hào): ST7LNB0V2Y0M6
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 8 MHz, MICROCONTROLLER, PDSO16
封裝: 0.150 INCH, PLASTIC, SOP-16
文件頁數(shù): 9/30頁
文件大?。?/td> 451K
代理商: ST7LNB0V2Y0M6
ST7LNB0V2Y0
Electrical characteristics
6.3
Operating conditions
Table 13.
General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VDD
Supply voltage
4.5
5.5
V
TA
Ambient temperature
-40
+85
°C
Table 14.
Operating conditions with low voltage detector (LVD)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIT+(LVD)
Reset release threshold
(VDD rise)
4.00
4.25
4.50
V
VIT-(LVD)
Reset generation threshold
(VDD fall)
3.80
4.10
4.30
Vhys
LVD voltage threshold
hysteresis
VIT+(LVD)-VIT-(LVD)
200
mV
VtPOR
VDD rise time rate
(1)
1.
Not tested in production. The VDD rise time rate condition is needed to ensure a correct device power-on
and LVD reset. When the VDD slope is outside these values, the LVD may not ensure a proper reset of the
MCU.
20
20000
s/V
tg(VDD)
Filtered glitch delay on VDD
Not detected by the LVD
150
ns
IDD(LVD) LVD/AVD current consumption
200
A
Table 15.
Operating conditions with the DiSEqC signalling
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fDiSEqC
DiSEqC tone frequency
17.6
22
26.4
kHz
VDiSEqC
DiSEqC tone voltage
150
650
mVPP
VBackward
13/18 volt backward
compatibility voltage
threshold(1)
1.
In backwards compatible mode, bus DC voltage is compared with 15 V. If it exceeds this voltage then it is
considered as 18 V else it is considered as 13 V.
15
V
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