參數(shù)資料
型號： ST7LNB0V2Y0M6
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 8 MHz, MICROCONTROLLER, PDSO16
封裝： 0.150 INCH, PLASTIC, SOP-16
文件頁數(shù)： 28/30頁
文件大?。?/td> 451K
代理商： ST7LNB0V2Y0M6
ST7LNB0V2Y0
ST7LNB0V2Y0 implementation
2
ST7LNB0V2Y0 implementation
Figure 3 shows a typical application circuit for the ST7LNB0V2Y0.
Figure 3.
ST7LNB0V2Y0 typical application circuit
1.
The divider chain connected to the DRX pin must have the following resistance values: 330K
and 100K.
2.
The reset circuitry linked to the RESET pin is optional. In fact the ST7LNB0V2Y0 has an internal voltage
level detector (LVD) which generates a static reset when the VDD supply is below a threshold voltage of
4.1 V.
3.
The DiSEqC signalling must have a tone frequency of 2 2kHz (
±20%) and an amplitude exceeding 150 mV
peak to peak.
4.
When the LVD is enabled (default state), it is mandatory not to connect a pull-up resistor. A 10 nF pull-
down capacitor is recommended to filter noise on the reset line.
ST7LNB0V2Y0
CONTROL
F-CONNECTOR
4.7K (4)
10n
100K
330K
LNB / SWITCHER
CONTROL
SBY
LNB / SWITCHER
(Uncommitted SW)
(Committed SW)
180pF
2N2222
OPTIONAL
VSS
VDD
RESET
DRX
OP5
OP6
OP7
OP8
NC
DTX
SBY
OP1
OP2
OP3
OP4
NC
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