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| 型號： | ST7LITE19F1M6 |
| 英文描述： | ST7LITE1 - 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY.DATA EEPROM. ADC. 4 TIMERS. SPI |
| 中文描述： | ST7LITE1 - 8單電壓閃存EEPROM的MEMORY.DATA位MCU。 ADC的。 4定時器。的SPI |
| 文件頁數(shù)： | 99/122頁 |
| 文件大小： | 1716K |
| 代理商： | ST7LITE19F1M6 |
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ST7LITE0, ST7SUPERLITE
99/122
13.9 CONTROL PIN CHARACTERISTICS
13.9.1 Asynchronous RESET Pin
T
A
= -40°C to 125°C, unless otherwise specified
Figure 82. Typical Application with RESET pin
6)7)8)
Notes:
1. Data based on characterization results, not tested in production.
2. The I
current sunk must always respect the absolute maximum rating specified in
Section 13.2.2
and the sum of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
3. The R
pull-up equivalent resistor is based on a resistive transistor. Specfied for voltages on RESET pin between
V
ILmax
and V
DD
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below t
h(RSTL)in
can be ignored.
5. The reset network protects the device against parasitic resets.
6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the V
IL
max. level specified in
section 13.9.1 on page 99
. Otherwise the reset will not be taken into account internally.
8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-p for example) is less than the absolute maximum value spec-
ified for I
INJ(RESET)
in
section 13.2.2 on page 79
.
Symbol
V
IL
V
IH
V
hys
Parameter
Conditions
Min
Typ
Max
0.3xV
DD
Unit
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
1)
V
0.7xV
DD
1
V
V
OL
Output low level voltage
2)
V
DD
=5V
I
IO
=+5mA T
A
≤
85°C
T
A
≥
85°C
0.5
1.0
1.2
0.4
0.5
80
V
I
IO
=+2mA T
A
≤
85°C
T
A
≥
85°C
0.2
R
ON
Pull-up equivalent resistor
3) 1)
V
DD
=5V
V
DD
=3V
Internal reset sources
20
40
TBD
30
k
t
w(RSTL)out
Generated reset pulse duration
t
h(RSTL)in
t
g(RSTL)in
μ
s
μ
s
ns
External reset pulse hold time
4)
Filtered glitch duration
5)
20
200
R
ON
0.01
μ
F
V
DD
0.01
μ
F
EXTERNAL
RESET
CIRCUIT
5)
USER
V
DD
4.7k
Required if LVD is disabled
Recommended
if LVD is disabled
ST72XXX
PULSE
GENERATOR
Filter
WATCHDOG
LVD RESET
INTERNAL
RESET
V
DD
1
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