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| 型號(hào)： | ST7LITE19F1M6 |
| 英文描述： | ST7LITE1 - 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY.DATA EEPROM. ADC. 4 TIMERS. SPI |
| 中文描述： | ST7LITE1 - 8單電壓閃存EEPROM的MEMORY.DATA位MCU。 ADC的。 4定時(shí)器。的SPI |
| 文件頁(yè)數(shù)： | 47/122頁(yè) |
| 文件大小： | 1716K |
| 代理商： | ST7LITE19F1M6 |
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ST7LITE0, ST7SUPERLITE
47/122
LITE TIMER
(Cont’d)
11.1.3 Functional Description
The value of the 8-bit counter cannot be read or
written by software. After an MCU reset, it starts
incrementing from 0 at a frequency of f
OSC
/32. A
counter overflow event occurs when the counter
rolls over from F9h to 00h. If f
OSC
= 8 MHz, then
the time period between two counter overflow
events is 1 ms. This period can be doubled by set-
ting the TB bit in the LTCSR register.
When the timer overflows, the TBF bit is set by
hardware and an interrupt request is generated if
the TBIE is set. The TBF bit is cleared by software
reading the LTCSR register.
11.1.3.1 Watchdog
The watchdog is enabled using the WDGE bit.
The normal Watchdog timeout is 2ms (@ = 8 MHz
f
OSC
), after which it then generates a reset.
To prevent this watchdog reset occuring, software
must set the WDGD bit. The WDGD bit is cleared
by hardware after t
WDG
. This means that software
must write to the WDGD bit at regular intervals to
prevent a watchdog reset occurring. Refer to
Fig-
ure 31
.
If the watchdog is not enabled immediately after
reset, the first watchdog timeout will be shorter
than 2ms, because this period is counted starting
from reset. Moreover, if a 2ms period has already
elapsed after the last MCU reset, the watchdog re-
set will take place as soon as the WDGE bit is set.
For these reasons, it is recommended to enable
the Watchdog immediately after reset or else to
set the WDGD bit before the WGDE bit so a
watchdog reset will not occur for at least 2ms.
Note:
Software can use the timebase feature to
set the WDGD bit at 1 or 2 ms intervals.
A Watchdog reset can be forced at any time by
setting the WDGRF bit. To generate a forced
watchdog reset, first watchdog has to be activated
by setting the WDGE bit and then the WDGRF bit
has to be set.
The WDGRF bit also acts as a flag, indicating that
the Watchdog was the source of the reset. It is au-
tomatically cleared after it has been read.
Caution:
When the WDGRF bit is set, software
must clear it, otherwise the next time the watchdog
is enabled (by hardware or software), the micro-
controller will be immediately reset.
Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGE bit in
the LTCSR is not used.
Refer to the Option Byte description in the "device
configuration and ordering information" section.
Using Halt Mode with the Watchdog (option)
If the Watchdog reset on HALT option is not se-
lected by option byte, the Halt mode can be used
when the watchdog is enabled.
In this case, the HALT instruction stops the oscilla-
tor. When the oscillator is stopped, the Lite Timer
stops counting and is no longer able to generate a
Watchdog reset until the microcontroller receives
an external interrupt or a reset.
If an external interrupt is received, the WDG re-
starts counting after 256 CPU clocks. If a reset is
generated, the Watchdog is disabled (reset state).
If Halt mode with Watchdog is enabled by option
byte (No watchdog reset on HALT instruction), it is
recommended before executing the HALT instruc-
tion to refresh the WDG counter, to avoid an unex-
pected WDG reset immediately after waking up
the microcontroller.
1
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