參數(shù)資料
型號(hào): ST7FLIT19BF1U6TR
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, QCC20
封裝: LEAD FREE, QFN-20
文件頁數(shù): 87/153頁
文件大?。?/td> 2862K
代理商: ST7FLIT19BF1U6TR
ST7LITE1xB
39/153
9 POWER SAVING MODES
9.1 INTRODUCTION
To give a large measure of flexibility to the applica-
tion in terms of power consumption, five main pow-
er saving modes are implemented in the ST7 (see
Slow
Wait (and Slow-Wait)
Active Halt
Auto Wake up From Halt (AWUFH)
Halt
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided or multiplied by 2
(fOSC2).
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
Figure 21. Power Saving Mode Transitions
9.2 SLOW MODE
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (fCPU) to
the available supply voltage.
SLOW mode is controlled by the SMS bit in the
MCCSR register which enables or disables Slow
mode.
In this mode, the oscillator frequency is divided by
32. The CPU and peripherals are clocked at this
lower frequency.
Note: SLOW-WAIT mode is activated when enter-
ing WAIT mode while the device is already in
SLOW mode.
Figure 22. SLOW Mode Clock Transition
POWER CONSUMPTION
WAIT
SLOW
RUN
ACTIVE HALT
High
Low
SLOW WAIT
AUTO WAKE UP FROM HALT
HALT
SMS
fCPU
NORMAL RUN MODE
REQUEST
fOSC
fOSC/32
fOSC
1
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