參數(shù)資料
型號(hào): ST7FLIT19BF1U6TR
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, QCC20
封裝: LEAD FREE, QFN-20
文件頁(yè)數(shù): 82/153頁(yè)
文件大小: 2862K
代理商: ST7FLIT19BF1U6TR
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)當(dāng)前第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)
ST7LITE1xB
34/153
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
7.6.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read/Write
Reset Value: 0110 0xx0 (6xh)
Bit 7 = LOCK32 PLL 32Mhz Locked Flag
This bit is set and cleared by hardware. It is set au-
tomatically when the PLL 32Mhz reaches its oper-
ating frequency
0: PLL32 not locked
1: PLL32 locked
Bits 6:5 = CR[1:0] RC Oscillator Frequency Ad-
justment bits
These bits, as well as CR[9:2] bits in the RCCR
register must be written immediately after reset to
adjust the RC oscillator frequency and to obtain an
accuracy of 1%. Refer to section 7.3 on page 25.
Bit 4 = WDGRF Watchdog Reset flag
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.
Bit 3 = LOCKED PLL Locked Flag
This bit is set and cleared by hardware. It is set au-
tomatically when the PLL reaches its operating fre-
quency.
0: PLL not locked
1: PLL locked
Bit 2 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (by reading). When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Bit 1 = AVDF Voltage Detector Flag
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is gen-
erated when the AVDF bit is set. Refer to Figure
19 and to Section 7.6.2.1 for additional details.
0: VDD over AVD threshold
1: VDD under AVD threshold
Bit 0 = AVDIE Voltage Detector Interrupt Enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag is
set. The pending interrupt information is automati-
cally cleared when software enters the AVD inter-
rupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
Application notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
PLL TEST REGISTER (PLLTST)
Read/Write
Reset Value: 0000 0000(00h)
Bit 7 : PLLdiv2 PLL clock divide by 2
This bit is read or write by software and cleared by
hardware after reset. This bit will divide the PLL
output clock by 2.
0 : PLL output clock
1 : Divide by 2 of PLL output clock
Note : Write of this bit will be effective after 2 Tcpu
cycles (if system clock is 8mhz) else 1 cycle (if
system clock is 4mhz) i.e. effective time is 250ns.
Bit 6:0 : Reserved , Must always be cleared
70
LOCK
32
CR1 CR0
WDG
RF
LOCKED LVDRF AVDF AVDIE
RESET Sources
LVDRF
WDGRF
External RESET pin
0
Watchdog
0
1
LVD
1
X
70
PLLdiv2
0
1
相關(guān)PDF資料
PDF描述
ST7FLITE09Y0M1 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16
ST7FLU05MAE 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8
ST7LNB0V2Y0M6 8-BIT, 8 MHz, MICROCONTROLLER, PDSO16
ST7LNB1Y0M6 8-BIT, EEPROM, 8 MHz, MICROCONTROLLER, PDSO16
ST7PL05Y0MB/XXXTRE 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO16
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST7FLIT19BU6TR 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST7FLIT19BY0B6 功能描述:8位微控制器 -MCU ST7LITE1xB 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST7FLIT19BY0BX 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
ST7FLIT19BY0M6 功能描述:8位微控制器 -MCU ST7LITE1xB 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST7FLIT19BY0MX 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI