參數(shù)資料
型號: ST7FLIT19BF1U6TR
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, QCC20
封裝: LEAD FREE, QFN-20
文件頁數(shù): 123/153頁
文件大小: 2862K
代理商: ST7FLIT19BF1U6TR
ST7LITE1xB
71/153
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
AUTORELOAD REGISTER (ATR1H)
Read / Write
Reset Value: 0000 0000 (00h)
AUTORELOAD REGISTER (ATR1L)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 11:0 = ATR1[11:0] Autoreload Register 1.
This is a 12-bit register which is written by soft-
ware. The ATR1 register value is automatically
loaded into the upcounter CNTR1 when an over-
flow occurs. The register value is used to set the
PWM frequency.
PWM OUTPUT CONTROL REGISTER
(PWMCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = OE[3:0] PWMx output enable.
These bits are set and cleared by software and
cleared by hardware after a reset.
0: PWM mode disabled. PWMx Output Alternate
Function disabled (I/O pin free for general pur-
pose I/O)
1: PWM mode enabled
PWMx CONTROL STATUS REGISTER
(PWMxCSR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:4= Reserved, must be kept cleared.
Bit 3 = OP_EN One Pulse Mode Enable
This bit is read/write by software and cleared by
hardware after a reset. This bit enables the One
Pulse feature for PWM2 and PWM3. (Only availa-
ble for PWM3CSR)
0: One Pulse mode disable for PWM2/3.
1: One Pulse mode enable for PWM2/3.
Bit 2 = OPEDGE One Pulse Edge Selection.
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the polarity
of the LTIC signal for One Pulse feature. This bit
will be effective only if OP_EN bit is set. (Only
available for PWM3CSR)
0: Falling edge of LTIC is selected.
1: Rising edge of LTIC is selected.
Bit 1 = OPx PWMx Output Polarity.
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the polarity
of the PWM signal.
0: The PWM signal is not inverted.
1: The PWM signal is inverted.
Bit 0 = CMPFx PWMx Compare Flag.
This bit is set by hardware and cleared by software
by reading the PWMxCSR register. It indicates
that the upcounter value matches the Active DCRx
register value.
0: Upcounter value does not match DCRx value.
1: Upcounter value matches DCRx value.
15
8
0
ATR11 ATR10
ATR9
ATR8
70
ATR7
ATR6
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
70
0OE3
0OE2
0OE10OE0
70
00
OP_EN
OPEDG
E
OPx
CMPFx
1
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