參數(shù)資料
型號: ST7FLIT19BF1U6TR
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, QCC20
封裝: LEAD FREE, QFN-20
文件頁數(shù): 102/153頁
文件大小: 2862K
代理商: ST7FLIT19BF1U6TR
ST7LITE1xB
52/153
I/O PORTS (Cont’d)
10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION
The I/O port register configurations are summa-
rised as follows.
Standard Ports
PA7:0, PB6:0
PC1:0 (multiplexed with OSC1,OSC2)
The selection between OSC1 or PC0 and OSC2 or
PC1 is done by option byte. Refer to section 15.1
on page 145. Interrupt capability is not available
on PC1:0.
Note: PCOR not implemented but p-transistor al-
ways active in output mode (refer to Figure 31 on
Interrupt Ports
Ports where the external interrupt capability is
selected using the EISR register
Table 10. Port Configuration (Standard ports)
Note: On ports where the external interrupt capability is selected using the EISR register, the configura-
tion will be as follows:
Table 11. I/O Port Register Map and Reset Values
MODE
DDR
OR
floating input
0
pull-up input
0
1
open drain output
1
0
push-pull output
1
MODE
DDR
floating input
0
push-pull output
1
MODE
DDR
OR
floating input
0
pull-up interrupt input
0
1
open drain output
1
0
push-pull output
1
Port
Pin name
Input
Output
OR = 0
OR = 1
OR = 0
OR = 1
Port A
PA7:0
floating
pull-up
open drain
push-pull
Port B
PB6:0
floating
pull-up
open drain
push-pull
Port
Pin name
Input
Output
OR = 0
OR = 1
OR = 0
OR = 1
Port A
PA7:0
floating
pull-up interrupt
open drain
push-pull
Port B
PB6:0
floating
pull-up interrupt
open drain
push-pull
Address
(Hex.)
Register
Label
76543
210
0000h
PADR
Reset Value
MSB
11
111
11
LSB
1
0001h
PADDR
Reset Value
MSB
00
000
00
LSB
0
1
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