參數(shù)資料
型號: ST7FLIT19BF1U6TR
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, QCC20
封裝: LEAD FREE, QFN-20
文件頁數(shù): 71/153頁
文件大小: 2862K
代理商: ST7FLIT19BF1U6TR
ST7LITE1xB
24/153
bled and the multiplication factor of 4 or 8 is select-
ed by 2 option bits.
– The x4 PLL is intended for operation with VDD in
the 2.7V to 3.3V range
– The x8 PLL is intended for operation with VDD in
the 3.3V to 5.5V range 1)
Refer to Section 15.1 for the option byte descrip-
tion.
If the PLL is disabled and the RC oscillator is ena-
bled, then fOSC = 1MHz.
If both the RC oscillator and the PLL are disabled,
fOSC is driven by the external clock.
Figure 12. PLL Output Frequency Timing
Diagram
When the PLL is started, after reset or wakeup
from Halt mode or AWUFH mode, it outputs the
clock after a delay of tSTARTUP.
When the PLL output signal reaches the operating
frequency, the LOCKED bit in the SICSCR register
is set. Full PLL accuracy (ACCPLL) is reached after
a stabilization time of tSTAB (see Figure 12 and
Refer to section 7.6.4 on page 34 for a description
of the LOCKED bit in the SICSR register.
Note 1:
It is possible to obtain fOSC = 4MHz in the 3.3V to
5.5V range with internal RC and PLL enabled by
selecting 1MHz RC and x8 PLL and setting the
PLLdiv2 bit in the PLLTST register (see section
4/8 x
freq.
LOCKED bit set
tSTAB
tLOCK
input
Out
p
ut
f
req.
tSTARTUP
t
1
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