參數(shù)資料
型號(hào): ST72C171
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCU with 8K FLASH, ADC, WDG, SPI, SCI, TIMERS SPGAs Software Programmable Gain Amplifiers, OP-AMP
中文描述: 8位8K閃存,ADC的,水分散粒劑,SPI和脊髓損傷,定時(shí)器SPGAs軟件可編程增益放大器,運(yùn)算放大器控制器
文件頁數(shù): 91/152頁
文件大?。?/td> 1384K
代理商: ST72C171
ST72C171
91/152
SERIAL PERIPHERAL INTERFACE
(Cont’d)
7.8.4 Functional Description
Figure 49
shows the serial peripheral interface
(SPI) block diagram.
This interface contains 3 dedicated registers:
– A Control Register (CR)
– A Status Register (SR)
– A Data Register (DR)
Refer to the CR, SR and DR registers in
Section
9.8.7
for the bit definitions.
7.8.4.1 Master Configuration
In a master configuration, the serial clock is gener-
ated on the SCK pin.
Procedure
– Select the SPR0 & SPR1 bits to define the se-
rial clock baud rate (see CR register).
– Select the CPOL and CPHA bits to define one
of the four relationships between the data
transfer and the serial clock (see
Figure 52
).
– The SS pin must be connected to a high level
signal during the complete byte transmit se-
quence.
– The MSTR and SPE bits must be set (they re-
main set only if the SS pin is connected to a
high level signal).
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Transmit sequence
The transmit sequence begins when a byte is writ-
ten the DR register.
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if the SPIE bit is set
and the I bit in the CCR register is cleared.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SR register while the SPIF bit
is set
2. A read to the DR register.
Note:
While the SPIF bit is set, all writes to the DR
register are inhibited until the SR register is read.
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