參數(shù)資料
型號(hào)： ST72C171
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCU with 8K FLASH, ADC, WDG, SPI, SCI, TIMERS SPGAs Software Programmable Gain Amplifiers, OP-AMP
中文描述： 8位8K閃存，ADC的，水分散粒劑，SPI和脊髓損傷，定時(shí)器SPGAs軟件可編程增益放大器，運(yùn)算放大器控制器
文件頁數(shù)： 38/152頁
文件大?。?/td> 1384K
代理商： ST72C171
ST72C171
38/152
7.3 OP-AMP MODULE
7.3.1 Introduction
The ST7 Op-Amp module is designed to cover
most types of microcontroller applications where
analog signal amplifiers are used.
It may be used to perform a a variety of functions
such as: differential voltage amplifier, comparator/
threshold detector, ADC zooming, impedance
adaptor, general purpose operational amplifier.
7.3.2 Main features
This module includes:
I
2 rail-to-rail SPGAs (Software Programmable
Gain Amplifier), and 1 stand alone rail-to-rail
Op-Amp that may be externally connected using
I/O pins
I
A band gap voltage reference
I
A programmable eight-step reference voltage
I
ART Timer PWM outputs internally connected
to SPGAs input 1 and 2.
I
SPGAs and Op-Amp outputs are internally
connected to the ADC inputs (Channel 8, 9 &
10).
I
Input offset compensation
7.3.3 General description
The module contains two SPGAs (OA1 & OA2)
and 1 stand alone operational amplifier (OA3) de-
pending on the device package. OA1 and OA2
each have associated circuitry for input and gain
selection. The third operational amplifier, OA3,
without input and gain selection circuitry, is availa-
ble in some devices (see device pin out descrip-
tion).
7.3.3.1 Inputs
The non-inverting input of OA1 or OA2 may be
connected to an I/O pin, to the band-gap reference
voltage, to an 8-step voltage reference or to the
analog ground.
The eight-step voltage reference uses a resistive
network in order to generate two voltages between
1/8 V
DD
and V
DD
(in 1/8 V
DD
steps) that can be
connected to the non-inverting input of the two SP-
GAs. These voltages may be used as programma-
ble thresholds with the corresponding SPGA used
as a comparator or, with the SPGA programmed to
have a gain of 2, 4 or 8, they may be used for ex-
tending the ADC precision (analog zooming).
The 2 inverting inputs of OA1 or OA2 may be used
to achieve this function. The input impedance of
these inputs is around 2K.
The ART Timer PWM resistive outputs are inter-
nally connected to OA1PIN and OA2PIN pins. The
PWM outputs are enabled by the PWMCR register
and the resistive outputs are selected by Miscella-
neous register 2. Refer to
Figure 28
.
The inverting input of OA1 or OA2 may be con-
nected to an I/O pin, to the analog ground or may
be left unconnected (in this case the SPGA can be
used as a repeater, with the output of the SPGA
connected to this input via the resistive loopback).
7.3.3.2 Outputs
The SPGA outputs are connected either to exter-
nal pins or, internally, to the ADC input (Channel 8
& 9).
The output value, digitized by a Schmitt trig-
ger, may be read by the application software or
may generate an interrupt.
The OA3 output is connected to an ADC input
(Channel 10).
7.3.3.3 Advanced features
The gain of OA1 or OA2 is programmed using an
internal resistive network. The possible values are:
1, 2, 4, 8 and 16. The internal resistive loopback
may also be de-activated in order to obtain the
open-loop gain (comparator) or to use the op-amp
with an external loopback network.
Input offset compensation
In a special calibration mode (autozero mode), the
negative input pin of OA1 or OA2 can be connect-
ed internally to the positive input pin. This mode al-
lows the measurement of the input offset voltage
of the SPGA using the ADC. This value may be
stored in RAM and subsequently used for offset
correction (for ADC conversions). Refer to Section
9.3.4.
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