參數(shù)資料
型號： ST72C171
廠商： 意法半導體
英文描述： 8-BIT MCU with 8K FLASH, ADC, WDG, SPI, SCI, TIMERS SPGAs Software Programmable Gain Amplifiers, OP-AMP
中文描述： 8位8K閃存，ADC的，水分散粒劑，SPI和脊髓損傷，定時器SPGAs軟件可編程增益放大器，運算放大器控制器
文件頁數(shù)： 80/152頁
文件大小： 1384K
代理商： ST72C171
ST72C171
80/152
SERIAL COMMUNICATIONS INTERFACE
(Cont’d)
7.7.4 Functional Description
The block diagram of the Serial Control Interface,
is shown in
Figure 47
. It contains 4 dedicated reg-
isters:
– Two control registers (CR1 & CR2)
– A status register (SR)
– A baud rate register (BRR)
Refer to the register descriptions in
Section 9.7.7
for the definitions of each bit.
7.7.4.1 Serial Data Format
Word length may be selected as being either 8 or 9
bits by programming the M bit in the CR1 register
(see
Figure 47
).
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 48. Word Length Programming
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Start
Bit
Stop
Bit
Next
Start
Bit
Idle Frame
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Start
Bit
Stop
Bit
Next
Start
Bit
Start
Bit
Idle Frame
Start
Bit
9-bit Word length (M bit is set)
8-bit Word length (M bit is reset)
Possible
Parity
Bit
Possible
Parity
Bit
Break Frame
Start
Bit
Extra
’1’
Data Frame
Break Frame
Start
Bit
Extra
’1’
Data Frame
Next Data Frame
Next Data Frame
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