參數(shù)資料
型號(hào): ST72C171
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCU with 8K FLASH, ADC, WDG, SPI, SCI, TIMERS SPGAs Software Programmable Gain Amplifiers, OP-AMP
中文描述: 8位8K閃存,ADC的,水分散粒劑,SPI和脊髓損傷,定時(shí)器SPGAs軟件可編程增益放大器,運(yùn)算放大器控制器
文件頁數(shù): 46/152頁
文件大?。?/td> 1384K
代理商: ST72C171
ST72C171
46/152
OP-AMP MODULE (
Cont’d
)
VOLTAGE REFERENCE CONTROL REGISTER
(OAVRCR)
Read/Write
Reset value: 0000 0000 (00h)
Bit 7 =
VR2E
:
VR2 Enable
This bit is set and reset by software. When the ref-
ererence voltage is selected (PS2[1:0] = 00 in the
OA2CR register) it connects V
SSA
(analog ground)
or Reference Voltage 2 (VR2) to the OA2 positive
input.
0: OA2 positive input is connected to V
SSA
1: OA2 positive input is connected to VR2 voltage
value
Bit 6:4 =
VR2[2:0]
Voltage selection for channel 2
of the 8-step reference voltage
These bits are set and reset by software, they
specify the Reference Voltage 2 (VR2) connected
to the OA2 positive input when PS2[1:0] = 00 in
the OA2CR register
.
.
Bit 3=
VR1E
VR1 Enable
This bit is set and reset by software. When the ref-
ererence voltage is selected (PS1[1:0] = 00 in the
OA1CR register) it connects V
SSA
(analog ground)
or Reference Voltage 1 (VR1) to the OA1 positive
input.
0: OA1 positive input is connected to V
SSA
1: OA1 positive input is connected to VR1 voltage
value
Bit 2:0 -
VR1[2:0]
Voltage selection for channel 1
of the 8-step reference voltage
These bits are set and reset by software, they
specify the Reference Voltage 1 (VR1) connected
to the OA1 positive input when PS1[1:0] = 00 in
the OA1CR register
.
Note:
When both VR2E and VR1E are reset, the
8-step voltage reference cell is disabled and en-
ters low power mode.
7
0
VR2E
VR22
VR21
VR20
VR1E
VR12
VR11
VR10
Reference
Voltage 2
0 (V
SSA
)
V
DDA
/8
2 x V
DDA
/8
3 x V
DDA
/8
4 x V
DDA
/8
5 x V
DDA
/8
6 x V
DDA
/8
7 x V
DDA
/8
V
DDA
VR2E
VR22
VR21
VR20
0
1
1
1
1
1
1
1
1
x
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
Reference
Voltage 1
0 (V
SSA
)
V
DDA
/8
2 x V
DDA
/8
3 x V
DDA
/8
4 x V
DDA
/8
5 x V
DDA
/8
6 x V
DDA
/8
7 x V
DDA
/8
V
DDA
VR1E
VR12
VR11
VR10
0
1
1
1
1
1
1
1
1
x
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
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