參數資料
型號: ST72C171
廠商: 意法半導體
英文描述: 8-BIT MCU with 8K FLASH, ADC, WDG, SPI, SCI, TIMERS SPGAs Software Programmable Gain Amplifiers, OP-AMP
中文描述: 8位8K閃存,ADC的,水分散粒劑,SPI和脊髓損傷,定時器SPGAs軟件可編程增益放大器,運算放大器控制器
文件頁數: 27/152頁
文件大?。?/td> 1384K
代理商: ST72C171
ST72C171
27/152
6 POWER SAVING MODES
6.1 INTRODUCTION
To give a large measure of flexibility to the applica-
tion in terms of power consumption, three main
power saving modes are implemented in the ST7
(see
Figure 20
).
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 2 (f
CPU
).
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the the oscil-
lator status.
Figure 20. Power Saving Mode Transitions
6.2 SLOW MODE
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (f
CPU
) to
the available supply voltage.
SLOW mode is controlled by three bits in the
MISCR1 register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (f
CPU
).
In this mode, the oscillator frequency can be divid-
ed by 4, 8, 16 or 32 instead of 2 in normal operat-
ing mode. The CPU and peripherals are clocked at
this lower frequency.
Note:
SLOW-WAIT mode is activated when enter-
ring the WAIT mode while the device is already in
SLOW mode.
Figure 21. SLOW Mode Clock Transitions
POWER CONSUMPTION
WAIT
SLOW
RUN
HALT
High
Low
SLOW WAIT
00
01
SMS
CP1:0
f
CPU
NEW SLOW
FREQUENCY
REQUEST
NORMAL RUN MODE
REQUEST
M
f
OSC
/2
f
OSC
/4
f
OSC
/8
f
OSC
/2
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