參數(shù)資料
型號(hào): ST10F273M-4Q3
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP144
封裝: 28 X 28 MM, 3.40 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-144
文件頁(yè)數(shù): 109/182頁(yè)
文件大?。?/td> 3222K
代理商: ST10F273M-4Q3
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Internal Flash memory
ST10F273M
5.4.2
Flash control register 0 high (FCR0H)
The Flash Control Register 0 High (FCR0H) together with the Flash Control Register 0 Low
(FCR0L) is used to enable and to monitor all the write operations on the IFlash. The user
has no access in write mode to the Test-Flash (B0TF). Moreover, the Test-Flash block is
seen by the user in Bootstrap mode only.
4LOCK
Flash registers access locked
When this bit is set, it means that the access to the Flash Control Registers
FCR0H/-FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC:
any read access to the registers will output invalid data (software trap 009Bh) and
any write access will be ineffective. LOCK bit is automatically set when the Flash
bit WMS is set.
This is the only bit the user can always access to detect the status of the Flash:
once it is found low, the rest of FCR0L and all the other Flash registers are
accessible by the user as well.
Note that FER content can be read when LOCK is low, but its content is updated
only when also BSYx bits are reset.
3:2
-
Reserved. These bits must be left to their reset value (0).
1BSYNVR
Busy of Non-Volatile Registers
This bit indicate that a write operation is running in the corresponding on “Non-
volatile registers”. They are automatically set when bit WMS is set. When this bit
is set every read access to the IFlash will output the value 009Bh (software trap),
while every write access to the IFlash will be ignored. At the end of the write
operation or during a Program Suspend this bit is automatically reset and the
IFlash returns to read mode. After a Program this bit is automatically set again.
0
-
Reserved. This bit must be left to its reset value (0).
Table 7.
FCR0L register description (continued)
Bit
Name
Function
FCR0H (0x0E 0002)
FCR
Reset value: 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WMS
SUSP
WPG
DWPG
SER
Reserved
SPR
DS
MOD
Reserved
RS
RW
-
RW
-
Table 8.
FCR0H register description
Bit
Name
Function
15
WMS
Write mode start
This bit must be set to start every write operation in the Flash module. At the end
of the write operation or during a Suspend, this bit is automatically reset. To
resume a suspended operation, this bit must be set again.
It is forbidden to set this bit if bit ERR of FER is high (the operation is not
accepted).
It is also forbidden to start a new write (program or erase) operation (by setting
WMS high) when bit SUSP of FCR0 is high. Resetting this bit by software has no
effect.
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