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參數(shù)資料
| 型號(hào)： | SSTUB32S869BHLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REGIST BUFF 14BIT DDR2 150BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Dec/2011 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 緩沖器 |
| Tx/Rx類型： | LVCMOS |
| 延遲時(shí)間： | 3.0ns |
| 電容 - 輸入： | 3.5pF |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 150-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 150-CABGA（8x13） |
| 包裝： | 帶卷 (TR) |
15
ICSSSTUB32S869B
Advance Information
1203—04/11/06
Error output load circuit and voltage measurement information (VDD =1.8 V± 0.1V)
All input pulses are supplied by generators having the following characteristics: PRR10 MHz;
Zo =50 ; input slew rate = 1 V/ns ± 20%, unless otherwise specified.
(1) CL includes probe and jig capacitance.
Figure 16 — Load circuit, error output measurements
Figure 17 — Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to RESET#
input
Figure 18 — Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect to clock
inputs
Figure 19 — Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to clock
inputs
CL = 10 pF
SEE NOTE (1)
VDD
OUT
DUT
TEST POINT
RL = 1 k
002aaa500
VCC/2
tPLH
VCC
0 V
0.15 V
VOH
0 V
Output
Waveform 2
LVCMOS
RESET
Input
002aaa501
VICR
tHL
VCC/2
VCC
VOL
Timing
Inputs
Output
Waveform 1
VI(PP)
VICR
002aaa502
VICR
tLH
VOH
0 V
Timing
Inputs
Output
Waveform 2
VI(PP)
VICR
0.15 V
002aaa503
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