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參數(shù)資料
| 型號： | SSTUB32S869BHLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REGIST BUFF 14BIT DDR2 150BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Dec/2011 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 緩沖器 |
| Tx/Rx類型： | LVCMOS |
| 延遲時間： | 3.0ns |
| 電容 - 輸入： | 3.5pF |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 150-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 150-CABGA（8x13） |
| 包裝： | 帶卷 (TR) |
12
ICSSSTUB32S869B
Advance Information
1203—04/11/06
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
MAX
fclock
Clock frequency
340
MHz
tACT
Differential inputs active time
10
ns
tINACT
Differential inputs inactive time
15
ns
tS
Setup time
Data before CLK
↑, CLK#↓
0.5
DCS0 before CLK
↑, CLK#↓,
CSR# high
0.7
Hold time
DCS#, DODT, DCKE and Q
after CK
↑, CK#↓
0.
7
ns
Hold time
PARIN1 after CK
↑, CK#↓
0.
5
ns
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
4 - CLK/CLK# signal input slew rate of 1V/ns.
SYMBOL
Notes:
tH
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
VDD = 1.8V ±0.1V
UNITS
PARAMETERS
ns
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
Symbol
Parameter
Measurement
Conditions
MIN
MAX
Units
Max input clock frequency
340
MHz
tPDM
Propagation delay, single
bit switching
CK
↑ to CK#↓ QN
1.2
1.9
ns
tLH
Low to High propagation
delay
CK
↑ to CK#↓ to
PTYERR#
1.2
3
ns
tHL
High to low propagation
delay
CK
↑ to CK#↓ to
PTYERR#
13
ns
tPDMSS
Propagation delay
simultaneous switching
CK
↑ to CK#↓ QN
2
ns
tPHL
High to low propagation
delay
RESET#
↓ to QN↓
3ns
tPLH
Low to High propagation
delay
RESET#
↓ to
PTYERR1#
↑
3ns
1. Guaranteed by design, not 100% tested in production.
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