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參數(shù)資料
| 型號(hào)： | SSTUB32S869BHLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 11/17頁(yè) |
| 文件大小： | 0K |
| 描述： | IC REGIST BUFF 14BIT DDR2 150BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Dec/2011 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 緩沖器 |
| Tx/Rx類型： | LVCMOS |
| 延遲時(shí)間： | 3.0ns |
| 電容 - 輸入： | 3.5pF |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 150-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 150-CABGA（8x13） |
| 包裝： | 帶卷 (TR) |
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3
ICSSSTUB32S869B
Advance Information
1203—04/11/06
Parity and Standby Function Table
RESET#
DCS#
CSR#
CK
CK#
of inputs = H
D1..…
D14
(1)
PARIN1
(2)
PPO1
(2)
PTYERR1#
(3)
HL
X
↑↓
Even
L
H
HL
X
↑↓
Odd
L
H
L
HL
X
↑↓
Even
H
L
HL
X
↑↓
Odd
H
L
H
HL
L
↑↓
Even
L
H
HL
L
↑↓
Odd
L
H
L
HL
L
↑↓
Even
H
L
HL
L
↑↓
Odd
H
L
H
HH
H
↑↓
X
PPOn0
PTYERRn0#
HX
X
L or H
X
PPOn0
PTYERRn0#
L
X or
floating
X or
floating
X or
floating
X or
floating
X or
floating
X or
floating
LH
NOTE 1
NOTE 2
NOTE 3
This transition assumes PTYERR1# is high at the crossing of CK going high and CK# going low.
If PTYERR1# is low, it stays latched low for two clock cycles or until RESET# is driven low. PARIN1 is
used to generate PPO1 and PTYERR1#.
Inputs
Output
Inputs D1, D4 and D4 are not included in this range.
PARIN1 arrives one (C1 = 0) or two (C = 1) clock cycles after data to which it applies.
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