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參數(shù)資料
| 型號： | SSTUB32S869BHLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REGIST BUFF 14BIT DDR2 150BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Dec/2011 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 緩沖器 |
| Tx/Rx類型： | LVCMOS |
| 延遲時間： | 3.0ns |
| 電容 - 輸入： | 3.5pF |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 150-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 150-CABGA（8x13） |
| 包裝： | 帶卷 (TR) |
Integrated
Circuit
Systems, Inc.
ICSSSTUB32S869B
Advance Information
1203—04/11/06
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
Recommended Application:
DDR2 Memory Modules
Provides complete DDR DIMM solution with
ICS97U877
Ideal for DDR2 400, 533 and 667
Product Features:
14-bit 1:2 registered buffer with parity check
functionality
Supports SSTL_18 JEDEC specification on data
inputs and outputs
50% more dynamic driver strength than standard
SSTU32864
Supports LVCMOS switching levels on C1 and
RESET# inputs
Low voltage operation
VDD = 1.7V to 1.9V
Available in 150 BGA package
Green packages available
14-Bit Configurable Registered Buffer for DDR2
Functionality Truth Table
Pin Configuration
150 Ball BGA
(Top View)
A
B
12345678
9
10
11
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Outputs
RESET#
DCS#
CSR#
CK
CK#
Dn,
DODT,
DCKE
Qn
QCS#
QODT,
QCKE
H
LL
L
H
LL
HH
L
H
L
L or H
X
Q0
H
LH
LL
L
H
LH
HH
L
H
L
H
L or H
X
Q0
H
HL
LL
H
L
H
HL
HH
H
L
L or H
X
Q0
HHH
L
Q0
HL
HHH
H
Q0
HH
H
L or H
X
Q0
L
X or
floating
X or
floating
X or
floating
X or
floating
X or
floating
LL
L
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
Inputs
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