參數(shù)資料
型號： SST89E54RC-33-C-PIE
廠商： Microchip Technology
文件頁數(shù)： 71/71頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 17KB FLASH 40PDIP
標(biāo)準(zhǔn)包裝： 9
系列： FlashFlex®
核心處理器： 8051
芯體尺寸： 8-位
速度： 33MHz
連通性： EBI/EMI，UART/USART
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 16KB（16K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
2011 Silicon Storage Technology, Inc.
DS25088A
10/11
9
FlashFlex MCU
SST89E52RC / SST89E54RC
Data Sheet
A Microchip Technology Company
To access the expanded RAM, the EXTRAM bit must be cleared and MOVX instructions must be used.
The extra 256 Bytes of memory is physically located on the chip and logically occupies the first 256
bytes of external memory (addresses 000H to FFH).
When EXTRAM = 0, the expanded RAM is indirectly addressed using the MOVX instruction in combina-
tion with any of the registers R0, R1 of the selected bank or DPTR. Accessing the expanded RAM does
not affect ports P0, P3.6 (WR#), P3.7 (RD#), or P2. With EXTRAM = 0, the expanded RAM can be
accessed as in the following example.
Expanded RAM Access (Indirect Addressing only):
MOVX@DPTR, A; DPTR contains 0A0H
DPTR points to 0A0H and data in “A” is written to address 0A0H of the expanded RAM rather than
external memory. Access to external memory higher than FFH using the MOVX instruction will access
external memory (0100H to FFFFH) and will perform in the same way as the standard 8051, with P0
and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals.
When EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 8051. Using
MOVX @Ri provides an 8-bit address with multiplexed data on Port 0. Other output port pins can be
used to output higher order address bits. This provides external paging capabilities. Using MOVX
@DPTR generates a 16-bit address. This allows external addressing up the 64K. Port 2 provides the
high-order eight address bits (DPH), and Port 0 multiplexes the low order eight address bits (DPL) with
data. Both MOVX @Ri and MOVX @DPTR generates the necessary read and write signals (P3.6 -
WR# and P3.7 - RD#) for external memory use. Table 2 shows external data memory RD#, WR# oper-
ation with EXTRAM bit.
The stack pointer (SP) can be located anywhere within the 256 bytes of internal RAM (lower 128 bytes
and upper 128 bytes). The stack pointer may not be located in any part of the expanded RAM.
Table 2: External Data Memory RD#, WR# with EXTRAM bit
MOVX @DPTR, A or MOVX A, @DPTR
MOVX @Ri, A or MOVX A, @Ri
AUXR
ADDR < 0100H
ADDR >= 0100H
ADDR = Any
EXTRAM = 0
RD# / WR# not asserted
RD# / WR# asserted
RD# / WR# not asserted1
1. Access limited to ERAM address within 0 to 0FFH.
EXTRAM = 1
RD# / WR# asserted
T0-0.0 25008
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