參數(shù)資料
型號(hào): SST89E54RC-33-C-PIE
廠商: Microchip Technology
文件頁(yè)數(shù): 31/71頁(yè)
文件大小: 0K
描述: IC MCU 8BIT 17KB FLASH 40PDIP
標(biāo)準(zhǔn)包裝: 9
系列: FlashFlex®
核心處理器: 8051
芯體尺寸: 8-位
速度: 33MHz
連通性: EBI/EMI,UART/USART
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
2011 Silicon Storage Technology, Inc.
DS25088A
10/11
37
FlashFlex MCU
SST89E52RC / SST89E54RC
Data Sheet
A Microchip Technology Company
Serial I/O
Full-Duplex, Enhanced UART
The device serial I/O port is a full-duplex port that allows data to be transmitted and received simultaneously
in hardware by the transmit and receive registers, respectively, while the software is performing other tasks.
The transmit and receive registers are both located in the Serial Data Buffer (SBUF) special function regis-
ter. Writing to the SBUF register loads the transmit register, and reading from the SBUF register obtains the
contents of the receive register.
The UART has four modes of operation which are selected by the Serial Port Mode Specifier (SM0 and
SM1) bits of the Serial Port Control (SCON) special function register. In all four modes, transmission is
initiated by any instruction that uses the SBUF register as a destination register. Reception is initiated
in mode 0 when the Receive Interrupt (RI) flag bit of the Serial Port Control (SCON) SFR is cleared
and the Reception Enable/ Disable (REN) bit of the SCON register is set. Reception is initiated in the
other modes by the incoming start bit if the REN bit of the SCON register is set.
Framing Error Detection
Framing Error Detection is a feature, which allows the receiving controller to check for valid stop bits in
modes 1, 2, or 3. Missing stops bits can be caused by noise in serial lines or from simultaneous trans-
mission by two CPUs.
Framing Error Detection is selected by going to the PCON register and changing SMOD0 = 1 (see Fig-
ure 7). If a stop bit is missing, the Framing Error bit (FE) will be set. Software may examine the FE bit
after each reception to check for data errors. After the FE bit has been set, it can only be cleared by
software. Valid stop bits do not clear FE. When FE is enabled, RI rises on the stop bit, instead of the
last data bit (see Figure 8 and Figure 9).
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