參數(shù)資料
型號: SPC563M64L5COAY
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, LEAD FREE, LQFP-144
文件頁數(shù): 66/140頁
文件大小: 1310K
代理商: SPC563M64L5COAY
Overview
SPC563M64
Doc ID 14642 Rev 6
SPI-like protocol. This SPI-like protocol is completely configurable for baud rate, polarity and
phase, frame length, chip select assertion, etc. Each bit in the frame may be configured to
serialize either eTPU channels, eMIOS channels or GPIO signals. The DSPI can be
configured to serialize data to an external device that implements the Microsecond Bus
protocol. There are two identical DSPI blocks on the SPC563Mxx MCU. The DSPI pins
support 5 V logic levels or Low Voltage Differential Signalling (LVDS) to improve high speed
operation.
The DSPIs have three configurations:
Serial peripheral interface (SPI) configuration where the DSPI operates as an up to 16-
bit SPI with support for queues
Enhanced deserial serial interface (DSI) configuration where DSPI serializes up to 32
bits with three possible sources per bit
eTPU, eMIOS, new virtual GPIO registers as possible bit source
Programmable inter-frame gap in continuous mode
Bit source selection allows microsecond bus downlink with command or data
frames up to 32 bits
Microsecond bus dual receiver mode
Combined serial interface (CSI) configuration where the DSPI operates in both SPI and
DSI configurations interleaving DSI frames with SPI frames, giving priority to SPI
frames
For queued operations, the SPI queues reside in system memory external to the DSPI. Data
transfers between the memory and the DSPI FIFOs are accomplished through the use of
the eDMA controller or through host software.
The DSPI supports these SPI features:
Full-duplex, synchronous transfers
Selectable LVDS Pads working at 40 MHz for SOUT, SIN and SCK pins
Master and Slave Mode
Buffered transmit operation using the TX FIFO with parameterized depth of 1 to 16
entries
Buffered receive operation using the RX FIFO with parameterized depth of 1 to 16
entries
TX and RX FIFOs can be disabled individually for low-latency updates to SPI queues
Visibility into the TX and RX FIFOs for ease of debugging
FIFO Bypass Mode for low-latency updates to SPI queues
Programmable transfer attributes on a per-frame basis:
Parameterized number of transfer attribute registers (from two to eight)
Serial clock with programmable polarity and phase
Various programmable delays:
PCS to SCK delay
SCK to PCS delay
Delay between frames
Programmable serial frame size of 4 to 16 bits, expandable with software control
Continuously held chip select capability
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參數(shù)描述
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SPC563M64L7COAY 制造商:STMicroelectronics 功能描述:JDP MICRO - Bulk
SPC563M64L7-ENG 制造商:STMicroelectronics 功能描述:ENG SAMPLES - Bulk
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SPC563MADPT176S 功能描述:32位微控制器 - MCU Socketed Mini Mod SPC563M QFP176 RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT