參數(shù)資料
型號: SPC563M64L5COAY
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, LEAD FREE, LQFP-144
文件頁數(shù): 56/140頁
文件大?。?/td> 1310K
代理商: SPC563M64L5COAY
SPC563M64
Overview
Doc ID 14642 Rev 6
The INTC provides the following features:
356 peripheral interrupt request sources
8 software setable interrupt request sources
9-bit vector addresses
Unique vector for each interrupt request source
Hardware connection to processor or read from register
Each interrupt source can be programmed to one of 16 priorities
Preemptive prioritized interrupt requests to processor
ISR at a higher priority preempts executing ISRs or tasks at lower priorities
Automatic pushing or popping of preempted priority to or from a LIFO
Ability to modify the ISR or task priority to implement the priority ceiling protocol for
accessing shared resources
Low latency—three clocks from receipt of interrupt request from peripheral to interrupt
request to processor
This device also includes a non-maskable interrupt (NMI) pin that bypasses the INTC and
multiplexing logic.
1.3.5
FMPLL
The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 20 MHz
crystal oscillator or external clock generator. Further, the FMPLL supports programmable
frequency modulation of the system clock. The PLL multiplication factor, output clock divider
ratio are all software configurable. The PLL has the following major features:
Input clock frequency from 4 MHz to 20 MHz
Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz, resulting in
system clock frequencies from 16 MHz to 80 MHz with granularity of 4 MHz or better
Reduced frequency divider (RFD) for reduced frequency operation without forcing the
PLL to relock
3 modes of operation
Bypass mode with PLL off
Bypass mode with PLL running (default mode out of reset)
PLL normal mode
Each of the three modes may be run with a crystal oscillator or an external clock
reference
Programmable frequency modulation
Modulation enabled/disabled through software
Triangle wave modulation up to 100 kHz modulation frequency
Programmable modulation depth (0% to 2% modulation depth)
Programmable modulation frequency dependent on reference frequency
Lock detect circuitry reports when the PLL has achieved frequency lock and
continuously monitors lock status to report loss of lock conditions
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