參數(shù)資料
型號: SPC563M64L5COAY
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, LEAD FREE, LQFP-144
文件頁數(shù): 58/140頁
文件大?。?/td> 1310K
代理商: SPC563M64L5COAY
SPC563M64
Overview
Doc ID 14642 Rev 6
The reset controller performs reset monitoring of internal and external reset sources, and
drives the RSTOUT pin. Communication between the SIU and the e200z335 CPU core is
via the crossbar switch. The SIU provides the following features:
System configuration
MCU reset configuration via external pins
Pad configuration control for each pad
Pad configuration control for virtual I/O via DSPI serialization
System reset monitoring and generation
Power-on reset support
Reset status register provides last reset source to software
Glitch detection on reset input
Software controlled reset assertion
External interrupt
11 interrupt requests
Rising or falling edge event detection
Programmable digital filter for glitch rejection
Critical Interrupt request
Non-Maskable Interrupt request
GPIO
GPIO function on 80 I/O pins
Virtual GPIO on 64 I/O pins via DSPI serialization (requires external
deserialization device)
Dedicated input and output registers for setting each GPIO and Virtual GPIO pin
Internal multiplexing
Allows serial and parallel chaining of DSPIs
Allows flexible selection of eQADC trigger inputs
Allows selection of interrupt requests between external pins and DSPI
1.3.8
ECSM
The error correction status module provides status information regarding platform memory
errors reported by error-correcting codes.
1.3.9
Flash
Devices in the SPC563Mxx family provide up to 1.5 MB of programmable, non-volatile, flash
memory. The non-volatile memory (NVM) can be used for instruction and/or data storage.
The flash module includes a Fetch Accelerator, that optimizes the performance of the flash
array to match the CPU architecture and provides single cycle random access to the flash
@ 80 MHz. The flash module interfaces the system bus to a dedicated flash memory array
controller. For CPU ‘loads’, DMA transfers and CPU instruction fetch, it supports a 64-bit
data bus width at the system bus port, and a 128-bit read data interface to flash memory.
The module contains a four-entry, 128-bit prefetch buffer and a prefetch controller which
prefetches sequential lines of data from the flash array into the buffer. Prefetch buffer hits
allow no-wait responses. Normal flash array accesses are registered and are forwarded to
the system bus on the following cycle, incurring three wait-states. Prefetch operations may
be automatically controlled, and are restricted to instruction fetch.
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