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參數(shù)資料
| 型號(hào)： | SPAKXC16Z1VFC20 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 20 MHz, MICROCONTROLLER, PQFP132 |
| 封裝： | PLASTIC, SMT-132 |
| 文件頁(yè)數(shù)： | 200/200頁(yè) |
| 文件大?。?/td> | 1383K |
| 代理商： | SPAKXC16Z1VFC20 |
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MC68HC16Z1
MOTOROLA
MC68HC16Z1TS/D
99
6 Standby RAM Module
This module contains a one Kbyte array of fast (two bus cycle) static RAM, which is especially useful
for system stacks and variable storage. SRAM can be mapped to any one Kbyte boundary in the ad-
dress map, but must not overlap the module control registers (overlap makes the registers inaccessi-
ble). Data can be read/written in bytes, words or long words. SRAM is powered by VDD in normal
operation. During power-down, SRAM contents are maintained by power from the VSTBY input. Power
switching between sources is automatic. An address map of the SRAM control registers follows.
Y = M111, where M is the logic state of the modmap (MM) bit in the SIMCR
6.1 SRAM Register Block
There are four SRAM control registers: the RAM module configuration register (RAMMCR), the RAM
test register (RAMTST), and the RAM array base address registers (RAMBAH/RAMBAL).
There is an 8-byte minimum register block size for the module. Unimplemented register addresses are
read as zeros. Writes have no effect.
6.2 SRAM Registers
The CPU16 in the MC68HC16Z1 operates only in supervisory mode. Access to the SRAM array is con-
trolled by the RASP field in RAMMCR. SRAM responds to both program and data space accesses
based on the value in the RASP field in RAMMCR. This allows code to be executed from RAM, and
permits the use of program counter relative addressing mode for operand fetches from the array.
Use RAMMCR to determine whether the RAM is in STOP mode or normal mode. It can also determine
in which space the array resides, and controls access to the base array registers. Reads of unimple-
mented bits always return zeros. Writes do not affect unimplemented bits.
STOP — Stop Control
0 = RAM array operates normally.
1 = RAM array enters low-power stop mode.
This bit controls whether the RAM array is in stop mode or normal operation. Reset state is one, leaving
the array configured for LPSTOP operation. In stop mode, the array retains its contents, but cannot be
read or written by the CPU. Because the CPU16 operates in supervisor mode, this bit can be read or
written at any time.
RLCK — RAM Base Address Lock
0 = SRAM base address registers are writable from IMB
1 = SRAM base address registers are locked
RLCK defaults to zero on reset. It can be written to one once.
Table 19 SRAM Address Map
Address
15
8
7
0
$YFFB00
RAM MODULE CONFIGURATION REGISTER (RAMMCR)
$YFFB02
RAM TEST REGISTER (RAMTST)
$YFFB04
RAM ARRAY BASE ADDRESS REGISTER HIGH (RAMBAH)
$YFFB06
RAM ARRAY BASE ADDRESS REGISTER LOW (RAMBAL)
$YFFB08
RESERVED
RAMMCR — RAM Module Configuration Register
$YFFB00
15
11
9
8
7
6
5
4
3
2
1
0
STOP
0
RLCK
0
RASP
NOT USED
RESET:
1
0
1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| SPAKXC301GC100D | 制造商:Motorola Inc 功能描述: |
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| SPAKXC309GC100A | 制造商:Motorola 功能描述:MOTOROLA |
| SPAKXC309VF100A | 功能描述:IC DSP 24BIT 100MHZ 196-MAPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:DSP563xx 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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