參數(shù)資料
型號(hào): SPAKXC16Z1VFC20
廠商: MOTOROLA INC
元件分類(lèi): 微控制器/微處理器
英文描述: 16-BIT, 20 MHz, MICROCONTROLLER, PQFP132
封裝: PLASTIC, SMT-132
文件頁(yè)數(shù): 113/200頁(yè)
文件大?。?/td> 1383K
代理商: SPAKXC16Z1VFC20
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MOTOROLA
MC68HC16Z1
20
MC68HC16Z1TS/D
Relative modes are used for branch and long branch instructions. A byte or word signed two's comple-
ment offset is added to the program counter if the branch condition is satisfied. The new PC value, con-
catenated with the PK field, is the effective address.
Post-modified index mode is used with the MOVB and MOVW instructions. A signed 8-bit offset is add-
ed to index register X after the effective address formed by XK and IX is used.
In M68HC11 systems, direct mode can be used to perform rapid accesses to RAM or I/O mapped into
page 0 ($0000 to $00FF), but the CPU16 uses the first 512 bytes of page 0 for exception vectors. To
compensate for the loss of direct mode, the ZK field and index register Z have been assigned reset ini-
tialization vectors. By resetting the ZK field to a chosen page, and using 8-bit unsigned index mode with
IZ, a programmer can access useful data structures anywhere in the address map.
2.6 Instruction Set
The CPU16 has an 8-bit instruction set. It uses a prebyte to support a multipage opcode map. This ar-
rangement makes it possible to fetch an 8-bit operand simultaneously with a Page 0 opcode. If a pro-
gram makes maximum use of 8-bit offset indexed addressing mode, it will have a significantly smaller
instruction space.
The instruction set is based on that of the M68HC11, but the opcode map has been rearranged to max-
imize performance with a 16-bit data bus. All M68HC11 instructions are supported by the CPU16, al-
though they may be executed differently. Most M68HC11 code runs on the CPU16 following
reassembly. However, take into account changed instruction times, the interrupt mask, and the new in-
terrupt stack frame.
The CPU16 has a full range of 16-bit arithmetic and logic instructions, including signed and unsigned
multiplication and division. New instructions have been added to support extended addressing and dig-
ital signal processing.
The following table is a summary of the CPU16 instruction set. Because it is only affected by a few in-
structions, the LSB of the condition code register is not shown in the table — instructions that affect the
interrupt mask and PK field are noted.
相關(guān)PDF資料
PDF描述
SPAKXC16Z1MFV20 16-BIT, 20 MHz, MICROCONTROLLER, PQFP144
SPAKXC16Z1CFC25 16-BIT, 25 MHz, MICROCONTROLLER, PQFP132
SPAKXC16Z1VFV20 16-BIT, 20 MHz, MICROCONTROLLER, PQFP144
SPAKXCF333CFT20 32-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP16
SPAKXCF333MFT20 32-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP16
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