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參數(shù)資料
| 型號(hào)： | SPAKXC16Z1VFC20 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 20 MHz, MICROCONTROLLER, PQFP132 |
| 封裝： | PLASTIC, SMT-132 |
| 文件頁(yè)數(shù)： | 150/200頁(yè) |
| 文件大?。?/td> | 1383K |
| 代理商： | SPAKXC16Z1VFC20 |
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MC68HC16Z1
MOTOROLA
MC68HC16Z1TS/D
53
3.5 External Bus Interface
The external bus interface (EBI) transfers information between the internal MCU bus and external de-
vices when the MC68HC16Z1 is operating in expanded modes. In fully expanded mode, the external
bus has 24 address lines and 16 data lines. In partially expanded mode, the external bus has 24 ad-
dress lines and 8 data lines. Because the CPU16 in the MC68HC16Z1 drives only 20 of the 24 IMB
address lines, ADDR[23:20] follow the output state of ADDR19.
The EBI provides dynamic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and
long-word transfers. Ports are accessed through the use of asynchronous cycles controlled by the data
transfer (SIZ1 and SIZ0) and data size acknowledge pins (DSACK1 and DSACK0). In fully expanded
mode, both 8-bit and 16-bit data ports can be accessed; in partially expanded mode, only 8-bit ports
can be accessed. Multiple bus cycles may be required for a transfer to an 8-bit port.
Port width is the maximum number of bits accepted or provided during a bus transfer. External devices
must follow the handshake protocol described below. Control signals indicate the beginning of the cycle,
the address space, the size of the transfer, and the type of cycle. The selected device controls the length
of the cycle. Strobe signals, one for the address bus and another for the data bus, indicate the validity
of an address and provide timing information for data. The EBI operates in an asynchronous mode for
any port width.
To add flexibility and minimize the necessity for external logic, MCU chip select logic can be synchro-
nized with EBI transfers. Chip select logic can also provide internally-generated bus control signals for
these accesses. Refer to 3.5.13 Chip Selects for more information.
3.5.1 Bus Control Signals
The CPU initiates a bus cycle by driving the address, size, function code, and read/write outputs. At the
beginning of the cycle, size signals SIZ0 and SIZ1 are driven along with the function code signals. The
size signals indicate the number of bytes remaining to be transferred during an operand cycle. They are
valid while the address strobe (AS) is asserted. The following table shows SIZ0 and SIZ1 encoding. The
read/write (R/W) signal determines the direction of the transfer during a bus cycle. This signal changes
state, when required, at the beginning of a bus cycle, and is valid while AS is asserted. R/W only tran-
sitions when a write cycle is preceded by a read cycle or vice versa. The signal can remain low for two
consecutive write cycles.
3.5.2 Function Codes
Function code signals FC[2:0] are automatically generated by the CPU16. The function codes can be
considered address extensions that automatically select one of eight address spaces to which an ad-
dress applies. These spaces are designated as either user or supervisor, and program or data spaces.
Because the CPU16 always operates in supervisor mode (FC2 always = 1), address spaces 0 to 3 are
not used. Address space 7 is designated CPU space. CPU space is used for control information not
normally associated with read or write bus cycles. Function codes are valid while AS is asserted.
Table 11 Size Signal Encoding
SIZ1
SIZ0
Transfer Size
0
1
Byte
1
0
Word
1
3 Byte
0
Long Word
Table 12 CPU16 Address Space Encoding
FC2
FC1
FC0
Address Space
1
0
Reserved
1
0
1
Data Space
1
0
Program Space
1
CPU Space
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| SPAKXC16Z1VFV20 | 16-BIT, 20 MHz, MICROCONTROLLER, PQFP144 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| SPAKXC301GC100D | 制造商:Motorola Inc 功能描述: |
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