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參數(shù)資料
| 型號： | SPAK56F802TA60 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, 60 MHz, OTHER DSP, PQFP32 |
| 封裝： | 7 X 7 MM, 0.80 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 38/39頁 |
| 文件大?。?/td> | 573K |
| 代理商： | SPAK56F802TA60 |
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8
56F802 Technical Data
MOTOROLA
2.2 Power and Ground Signals
2.3 Interrupt and Program Control Signals
Table 3. Power Inputs
No. of Pins
Signal Name
Signal Description
2
VDD
Power—These pins provide power to the internal structures of the chip, and
should all be attached to VDD.
1
VDDA
Analog Power—This pin is a dedicated power pin for the analog portion of the
chip and should be connected to a low noise 3.3V supply.
Table 4. Grounds
No. of Pins
Signal Name
Signal Description
2
VSS
GND—These pins provide grounding for the internal structures of the chip, and
should all be attached to VSS.
1
VSSA
Analog Ground—This pin supplies an analog ground.
1
TCS
TCS—This Schmitt pin is reserved for factory use and must be tied to VSS for
normal use. In block diagrams, this pin is considered an additional VSS.
Table 5. Supply Capacitors and VPP
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
2
VCAPC
Supply
VCAPC—Connect each pin to a 2.2
F or greater bypass
capacitor in order to bypass the core logic voltage regulator
(required for proper chip operation). For more information, refer to
Table 6. Program Control Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
RESET
Input
(Schmitt)
Input
Reset—This input is a direct hardware reset on the processor.
When RESET is asserted low, the hybrid controller is initialized
and placed in the Reset state. A Schmitt trigger input is used for
noise immunity. When the RESET pin is deasserted, the initial
chip operating mode is latched from the EXTBOOT pin. The
internal reset signal will be deasserted synchronous with the
internal clocks, after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST should
be asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case,
assert RESET, but do not assert TRST.
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