參數(shù)資料
型號(hào): SPAK56F802TA60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 0-BIT, 60 MHz, OTHER DSP, PQFP32
封裝: 7 X 7 MM, 0.80 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-32
文件頁數(shù): 14/39頁
文件大?。?/td> 573K
代理商: SPAK56F802TA60
Clock Operation
MOTOROLA
56F802 Technical Data
21
Figure 10. Typical Relaxation Oscillator Frequency vs. Trim Value @ 25oC
3.5.2
Phase Locked Loop Timing
Table 20. PLL Timing
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency for the PLL1
1.
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2.
ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter
in the User Manual. ZCLK = fop
3.
Will not exceed 60MHz for the DSP56F802TA60 device.
4.
This is the minimum time required after the PLL setup is changed to ensure reliable operation.
fosc
48
10
MHz
PLL output frequency2
fout/2
40
803
MHz
PLL stabilization time4 0o to +85oC
tplls
10
ms
PLL stabilization time4 -40o to 0oC
tplls
100
200
ms
0
102030 40 50
60 70 80
90 A0 B0 C0 D0 E0
F0
5
6
7
8
9
10
11
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