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參數(shù)資料
| 型號： | SPAK56F802TA60 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, 60 MHz, OTHER DSP, PQFP32 |
| 封裝： | 7 X 7 MM, 0.80 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 23/39頁 |
| 文件大?。?/td> | 573K |
| 代理商： | SPAK56F802TA60 |
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56F802 Description
MOTOROLA
56F802 Technical Data
3
Computer-Operating Properly (COP) watchdog timer
External interrupts via GPIO
Trimmable on-chip relaxation oscillator
External reset pin for hardware reset
JTAG/On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Locked Loop-based frequency synthesizer for the hybrid controller
core clock
1.1.4
Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
Uses a single 3.3V power supply
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
Integrated power supervisor
1.2 56F802 Description
The 56F802 is a member of the 56800 core-based family of hybrid controllers. It combines, on a single
chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of
peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility,
and compact program code, the 56F802 is well-suited for many applications. The 56F802 includes many
peripherals that are especially useful for applications such as motion control, home appliances, encoders,
tachometers, limit switches, power supply and control, engine management, and industrial control for
power, lighting, automation and HVAC.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The 56F802 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F802 also provides and up to 4
General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
The 56F802 controller includes 8K words (16-bit) of Program Flash and 2K words of Data Flash (each
programmable through the JTAG port) with 1K words of both Program and Data RAM. A total of 2K words
of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines that can
be used to program the main Program and Data Flash memory areas. Both Program and Data Flash
memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory
can also be either bulk or page erased.
A key application-specific feature of the 56F802 is the inclusion of a Pulse Width Modulator (PWM)
module. This modules incorporates six complementary, individually programmable PWM signal outputs to
enhance motor control functionality. Complementary operation permits programmable dead-time insertion,
and separate top and bottom output polarity control. The up-counter value is programmable to support a
continuously variable PWM frequency. Both edge- and center-aligned synchronous pulse width control (0%
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