參數(shù)資料
型號(hào)： SMJ320C6701GLPW16
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 166.66 MHz, OTHER DSP, CBGA429
封裝： 27 X 27 MM, CERAMIC, MO-156, BGA-429
文件頁(yè)數(shù)： 62/63頁(yè)
文件大?。?/td> 909K
代理商： SMJ320C6701GLPW16
SMJ320C6701
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SGUS060 DECEMBER 2007
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Signal Descriptions
SIGNAL
TYPE
DESCRIPTION
NAME
NO.
TYPE
DESCRIPTION
CLOCK/PLL
CLKIN
A14
I
Clock Input
CLKOUT1
Y6
O
Clock output at full device speed
CLKOUT2
V9
O
Clock output at half of device speed
CLKMODE1
B17
I
Clock mode select
CLKMODE0
C17
I
Selects whether the output clock frequency = input clock freq x4 or x1
PLLFREQ3
C13
PLL frequency range (3, 2, and 1)
PLLFREQ2
G11
I
The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ pins.
PLLFREQ1
F11
I
PLLV
D12
A§
PLL analog VCC connection for the low-pass filter
PLLG
G10
A§
PLL analog GND connection for the low-pass filter
PLLF
C12
A§
PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
TMS
K19
I
JTAG test port mode select (features an internal pull-up)
TDO
R12
O/Z
JTAG test port data out
TDI
R13
I
JTAG test port data in (features an internal pull-up)
TCK
M20
I
JTAG test port clock
TRST
N18
I
JTAG test port reset (features an internal pull-down)
EMU1
R20
I/O/Z
Emulation pin 1, pull-up with a dedicated 20-k
resistor
EMU0
T18
I/O/Z
Emulation pin 0, pull-up with a dedicated 20-k
resistor
RESET AND INTERRUPTS
RESET
J20
I
Device reset
NMI
K21
I
Nonmaskable interrupt
Edge-driven (rising edge)
EXT_INT7
R16
EXT_INT6
P20
I
External interrupts
EXT_INT5
R15
I
External interrupts
Edge-driven (rising edge)
EXT_INT4
R18
Edge-driven (rising edge)
IACK
R11
O
Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3
T19
Active interrupt identification number
INUM2
T20
O
Active interrupt identification number
Valid during IACK for all active interrupts (not just external)
INUM1
T14
O
Valid during IACK for all active interrupts (not just external)
Encoding order follows the interrupt service fetch packet ordering
INUM0
T16
Encoding order follows the interrupt service fetch packet ordering
LITTLE ENDIAN/BIG ENDIAN
LENDIAN
G20
I
If high, selects little-endian byte/half-word addressing order within a word
If low, selects big-endian addressing
POWER DOWN STATUS
PD
D19
O
Power-down mode 2 or 3 (active if high)
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
PLLV and PLLG signals are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect
those pins.
§ A = Analog Signal (PLL Filter)
For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-k resistor. For boundary scan, pull down EMU1 and EMU0
with a dedicated 20-k
resistor.
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