參數(shù)資料
型號： SMJ320C6701GLPW16
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號處理
英文描述： 32-BIT, 166.66 MHz, OTHER DSP, CBGA429
封裝： 27 X 27 MM, CERAMIC, MO-156, BGA-429
文件頁數(shù)： 52/63頁
文件大小： 909K
代理商： SMJ320C6701GLPW16
SMJ320C6701
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SGUS060 DECEMBER 2007
56
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 35)
NO.
’C6701-14
’C6701-16
UNIT
NO.
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
4
tsu(DRV-CKXH) Setup time, DR valid before CLKX high
12
2 3P
ns
5
th(CKXH-DRV)
Hold time, DR valid after CLKX high
4
5 + 6P
ns
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1
(see Figure 35)
NO.
PARAMETER
’C6701-14
’C6701-16
UNIT
NO.
PARAMETER
MASTER§
SLAVE
UNIT
MIN
MAX
MIN
MAX
1
th(CKXH-FXL)
Hold time, FSX low after CLKX high
T 4
T + 4
ns
2
td(FXL-CKXL)
Delay time, FSX low to CLKX low#
H 4
H + 4
ns
3
td(CKXL-DXV)
Delay time, CLKX low to DX valid
4
3P + 1
5P + 17
ns
6
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX high
*H 2
*H + 3
ns
7
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit
from FSX high
*P + 4
*3P + 17
ns
8
td(FXL-DXV)
Delay time, FSX low to DX valid
2P + 1
4P + 13
ns
*This parameter is not tested.
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T =
CLKX period = (1 + CLKGDV) * S
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
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