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參數(shù)資料
| 型號： | SMJ320C6701GLPW16 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 166.66 MHz, OTHER DSP, CBGA429 |
| 封裝： | 27 X 27 MM, CERAMIC, MO-156, BGA-429 |
| 文件頁數(shù)： | 46/63頁 |
| 文件大小： | 909K |
| 代理商： | SMJ320C6701GLPW16 |
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SMJ320C6701
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SGUS060 DECEMBER 2007
50
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics for McBSP§ (see Figure 31)
NO.
PARAMETER
’C6701-14
’C6701-16
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
1
td(CKSH-CKRXH)
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
3
15
ns
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
2P
ns
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X int
C 1
C + 1
ns
4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
CLKR int
4
ns
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX int
4
5
ns
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX ext
*3
*16
ns
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX int
*3
*2
ns
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high
CLKX ext
*2
*9
ns
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid.
CLKX int
2
4
ns
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid.
CLKX ext
3
16
ns
14
td(FXH-DXV)
Delay time, FSX high to DX valid.
FSX int
*2
*4
ns
14
td(FXH-DXV)
Delay time, FSX high to DX valid.
ONLY applies when in data delay 0 (XDATDLY = 00b) mode.
FSX ext
*2
*10
ns
CLKRP = CLKXP = FSRP = FSXP = 0 in the pin control register (PCR). If polarity of any of the signals is inverted, then the timing references
of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
§ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
C = H or L
S =
sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
*This parameter is not tested.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SMJ320C6701S14 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SMJ320C6701S16 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SMJ320C6701-SP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SMJ320C6701W14 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SMJ320C6701W16 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
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