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參數(shù)資料
| 型號： | SMJ320C6701GLPW16 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 166.66 MHz, OTHER DSP, CBGA429 |
| 封裝： | 27 X 27 MM, CERAMIC, MO-156, BGA-429 |
| 文件頁數(shù)： | 28/63頁 |
| 文件大?。?/td> | 909K |
| 代理商： | SMJ320C6701GLPW16 |
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SMJ320C6701
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SGUS060 DECEMBER 2007
34
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK)
(see Figure 14)
NO.
’C6701-14
’C6701-16
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
7
tsu(EDV-SSCLKH)
Setup time, read EDx valid before SSCLK high
2.6
2.5
ns
8
th(SSCLKH-EDV)
Hold time, read EDx valid after SSCLK high
1.5
ns
switching characteristics for synchronous-burst SRAM cycles (full-rate SSCLK)
(see Figure 14 and Figure 15)
NO.
PARAMETER
’C6701-14
’C6701-16
UNIT
NO.
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1
tosu(CEV-SSCLKH)
Output setup time, CEx valid before SSCLK high
0.5P 1.5
0.5P 1.3
ns
2
toh(SSCLKH-CEV)
Output hold time, CEx valid after SSCLK high
0.5P 2.5
0.5P 2.3
ns
3
tosu(BEV-SSCLKH)
Output setup time, BEx valid before SSCLK high
0.5P 1.6
ns
4
toh(SSCLKH-BEIV)
Output hold time, BEx invalid after SSCLK high
0.5P 2.5
0.5P 2.3
ns
5
tosu(EAV-SSCLKH)
Output setup time, EAx valid before SSCLK high
0.5P 1.7
ns
6
toh(SSCLKH-EAIV)
Output hold time, EAx invalid after SSCLK high
0.5P 2.5
ns
9
tosu(ADSV-SSCLKH)
Output setup time, SSADS valid before SSCLK high
0.5P 1.5
0.5P 1.3
ns
10
toh(SSCLKH-ADSV)
Output hold time, SSADS valid after SSCLK high
0.5P 2.5
0.5P 2.3
ns
11
tosu(OEV-SSCLKH)
Output setup time, SSOE valid before SSCLK high
0.5P 1.5
0.5P 1.3
ns
12
toh(SSCLKH-OEV)
Output hold time, SSOE valid after SSCLK high
0.5P 2.5
ns
13
tosu(EDV-SSCLKH)
Output setup time, EDx valid before SSCLK high
0.5P 1.5
0.5P 1.3
ns
14
toh(SSCLKH-EDIV)
Output hold time, EDx invalid after SSCLK high
0.5P 2.5
ns
15
tosu(WEV-SSCLKH)
Output setup time, SSWE valid before SSCLK high
0.5P 1.5
0.5P 1.3
ns
16
toh(SSCLKH-WEV)
Output hold time, SSWE valid after SSCLK high
0.5P 2.5
0.5P 2.3
ns
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter.
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN
low) for all output hold times.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SMJ320C6701S14 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SMJ320C6701S16 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SMJ320C6701-SP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SMJ320C6701W14 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SMJ320C6701W16 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
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