參數(shù)資料
型號(hào)： SMJ320C6701GLPW16
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 166.66 MHz, OTHER DSP, CBGA429
封裝： 27 X 27 MM, CERAMIC, MO-156, BGA-429
文件頁(yè)數(shù)： 25/63頁(yè)
文件大?。?/td> 909K
代理商： SMJ320C6701GLPW16
SMJ320C6701
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SGUS060 DECEMBER 2007
31
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics for CLKOUT2 (see Figure 10)
NO.
PARAMETER
’C6701-14
’C6701-16
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
1
tc(CKO2)
Cycle time, CLKOUT2
*2P 0.7
*2P + 0.7
ns
2
tw(CKO2H)
Pulse duration, CLKOUT2 high
*P 0.7
*P + 0.7
ns
3
tw(CKO2L)
Pulse duration, CLKOUT2 low
*P 0.7
*P + 0.7
ns
4
tt(CKO2)
Transition time, CLKOUT2
*0.6
ns
P = 1/CPU clock frequency in ns.
*This parameter is not tested.
CLKOUT2
1
2
3
4
Figure 10. CLKOUT2 Timings
SDCLK, SSCLK timing parameters
SDCLK timing parameters are the same as CLKOUT2 parameters.
SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK
configuration.
switching characteristics for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1
(see Figure 11)
NO.
PARAMETER
’C6701-14
’C6701-16
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
1
td(CKO1-SSCLK)
Delay time, CLKOUT1 edge to SSCLK edge
0.8
3.4
ns
2
td(CKO1-SSCLK1/2)
Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate)
1.0
3.0
ns
3
td(CKO1-CKO2)
Delay time, CLKOUT1 edge to CLKOUT2 edge
1.5
2.5
ns
4
td(CKO1-SDCLK)
Delay time, CLKOUT1 edge to SDCLK edge
1.5
1.9
ns
4
3
2
1
CLKOUT1
SSCLK
SSCLK (1/2rate)
CLKOUT2
SDCLK
Figure 11. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1
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