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參數(shù)資料
| 型號： | SMJ320C6701GLPW16 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 166.66 MHz, OTHER DSP, CBGA429 |
| 封裝： | 27 X 27 MM, CERAMIC, MO-156, BGA-429 |
| 文件頁數(shù)： | 32/63頁 |
| 文件大?。?/td> | 909K |
| 代理商： | SMJ320C6701GLPW16 |
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SMJ320C6701
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SGUS060 DECEMBER 2007
38
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles (see Figure 18)
NO.
’C6701-14
’C6701-16
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
7
tsu(EDV-SDCLKH)
Setup time, read EDx valid before SDCLK high
2
ns
8
th(SDCLKH-EDV)
Hold time, read EDx valid after SDCLK high
3
ns
switching characteristics for synchronous DRAM cycles (see Figure 18Figure 23)
NO.
PARAMETER
’C6701-14
’C6701-16
UNIT
NO.
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1
tosu(CEV-SDCLKH)
Output setup time, CEx valid before SDCLK high
1.5P 5
1.5P 4
ns
2
toh(SDCLKH-CEV)
Output hold time, CEx valid after SDCLK high
0.5P 1.9
0.5P 1.5
ns
3
tosu(BEV-SDCLKH)
Output setup time, BEx valid before SDCLK high
1.5P 5
1.5P 4
ns
4
toh(SDCLKH-BEIV)
Output hold time, BEx invalid after SDCLK high
0.5P 1.9
0.5P 1.5
ns
5
tosu(EAV-SDCLKH)
Output setup time, EAx valid before SDCLK high
1.5P 5
1.5P 4
ns
6
toh(SDCLKH-EAIV)
Output hold time, EAx invalid after SDCLK high
0.5P 1.9
0.5P 1.5
ns
9
tosu(SDCAS-SDCLKH)
Output setup time, SDCAS valid before SDCLK
high
1.5P 5
1.5P 4
ns
10
toh(SDCLKH-SDCAS)
Output hold time, SDCAS valid after SDCLK high
0.5P 1.9
0.5P 1.5
ns
11
tosu(EDV-SDCLKH)
Output setup time, EDx valid before SDCLK high
1.5P 5
1.5P 4
ns
12
toh(SDCLKH-EDIV)
Output hold time, EDx invalid after SDCLK high
0.5P 1.9
0.5P 1.5
ns
13
tosu(SDWE-SDCLKH)
Output setup time, SDWE valid before SDCLK
high
1.5P 5
1.5P 4
ns
14
toh(SDCLKH-SDWE)
Output hold time, SDWE valid after SDCLK high
0.5P 1.9
0.5P 1.5
ns
15
tosu(SDA10V-SDCLKH)
Output setup time, SDA10 valid before SDCLK
high
1.5P 5
1.5P 4
ns
16
toh(SDCLKH-SDA10IV)
Output hold time, SDA10 invalid after SDCLK
high
0.5P 1.9
0.5P 1.5
ns
17
tosu(SDRAS-SDCLKH)
Output setup time, SDRAS valid before SDCLK
high
1.5P 5
1.5P 4
ns
18
toh(SDCLKH-SDRAS)
Output hold time, SDRAS valid after SDCLK high
0.5P 1.9
0.5P 1.5
ns
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter.
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SMJ320C6701S14 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SMJ320C6701S16 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SMJ320C6701-SP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SMJ320C6701W14 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SMJ320C6701W16 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
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