- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98084 > SMJ320C6701GLPW16 (TEXAS INSTRUMENTS INC) 32-BIT, 166.66 MHz, OTHER DSP, CBGA429 PDF資料下載
參數(shù)資料
| 型號： | SMJ320C6701GLPW16 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 166.66 MHz, OTHER DSP, CBGA429 |
| 封裝： | 27 X 27 MM, CERAMIC, MO-156, BGA-429 |
| 文件頁數(shù)： | 37/63頁 |
| 文件大?。?/td> | 909K |
| 代理商： | SMJ320C6701GLPW16 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當(dāng)前第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁
SMJ320C6701
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SGUS060 DECEMBER 2007
42
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
HOLD/HOLDA TIMING
timing requirements for the hold/hold acknowledge cycles (see Figure 24)
NO.
’C6701-14
’C6701-16
UNIT
NO.
MIN
MAX
UNIT
1
tsu(HOLDH-CKO1H)
Setup time, HOLD high before CLKOUT1 high
5
ns
2
th(CKO1H-HOLDL)
Hold time, HOLD low after CLKOUT1 high
2
ns
HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle.
Thus, HOLD can be an asynchronous input.
switching characteristics for the hold/hold acknowledge cycles (see Figure 24)
NO.
PARAMETER
’C6701-14
’C6701-16
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
3
tR(HOLDL-EMHZ)
Response time, HOLD low to EMIF high impedance
4P
§
ns
4
tR(EMHZ-HOLDAL)
Response time, EMIF high impedance to HOLDA low
2P
ns
5
tR(HOLDH-HOLDAH)
Response time, HOLD high to HOLDA high
4P
7P
ns
6
td(CKO1H-HOLDAL)
Delay time, CLKOUT1 high to HOLDA valid
1
8
ns
7
td(CKO1H-BHZ)
Delay time, CLKOUT1 high to EMIF Bus high impedance
*1
*8
ns
8
td(CKO1H-BLZ)
Delay time, CLKOUT1 high to EMIF Bus low impedance
*1
*12
ns
9
tR(HOLDH-BLZ)
Response time, HOLD high to EMIF Bus low impedance
3P
6P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
§ All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write
with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then
the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting the NOHOLD = 1.
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
*This parameter is not tested.
DSP Owns Bus
External Requester
DSP Owns Bus
’C6701
Ext Req
’C6701
8
7
3
4
6
1
2
CLKOUT1
HOLD
HOLDA
EMIF Bus
1
5
9
2
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
Figure 24. HOLD/HOLDA Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SMJ34010-50FDM | GRAPHICS PROCESSOR, CQCC68 |
| SMJ34010-40GBM | GRAPHICS PROCESSOR, CPGA68 |
| SMJ34010FDM | GRAPHICS PROCESSOR, CQCC68 |
| SMJ9914AFDS | IEEE 488 (GPIB) BUS CONTROLLER, CQCC44 |
| SMQ320C32PCM50 | 32-BIT, 50 MHz, OTHER DSP, PQFP144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SMJ320C6701S14 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SMJ320C6701S16 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SMJ320C6701-SP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SMJ320C6701W14 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SMJ320C6701W16 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。