參數(shù)資料
型號: SL811S
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 總線控制器
英文描述: USB Dual Speed Slave Controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC28
封裝: PLASTIC, LCC-28
文件頁數(shù): 14/27頁
文件大小: 181K
代理商: SL811S
SL811S/T
Document #: 38-08009 Rev. **
Page 14 of 27
5.4.5
Register indicates currently selected data set for each endpoint.
Current Data Set Register, Address [0EH]
5.4.6
Read only Register contains the 7 low order bits of Frame Number in positions: bit 7
1. Bit 0 is undefined. Register is updated
when a SOF packet is received. User should not write to this register.
SOF Low Register, Address [15h]
5.4.7
Read only Register contains the 4 low order bits of Frame Number in positions: bit 7
4. Bits 3
0 are undefined, and should be
masked when read by the user. Register is updated when a SOF packet is received. User should not write to this register.
SOF High Register, Address [16h]
5.4.8
Register contains the low order 8-bits of
DMA
count.
DMA
total count is the total number of bytes to be transferred between a
peripheral to the SL811S/T. The count may sometimes require up to 16-bits, thus the count is represented in two registers: Total
Count Low, and Total Count High. EP3 is only supported with DMA operation.
DMA Total Count Low Register, Address [35h]
5.4.9
Register contains the High order 8-bits of
DMA
count.
When written, this register enables DMA
if the DMA Enable bit is set in
the Control Register.
User should always write Low Count Register first, followed by a write to High Count Register even if high
count is 00H.
DMA Total Count High Register, Address [36h]
6.0
SL811S/T Physical Connection
The diagram below indicates the pin assignments for the SL811S 28-pin PLCC Package.
Bit Position
Bit Name
Function
0
Endpoint 0
Endpoint 0a = 0, Endpoint 0b = 1
1
Endpoint 1
Endpoint 1a = 0, Endpoint 1b = 1
2
Endpoint 2
Endpoint 2a = 0, Endpoint 2b = 1
3
Endpoint 3
Endpoint 3a = 0, Endpoint 3b = 1
4-7
Reserved
For the Host
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