參數(shù)資料
型號(hào)： SL811S
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： USB Dual Speed Slave Controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQCC28
封裝： PLASTIC, LCC-28
文件頁數(shù)： 13/27頁
文件大?。?/td> 181K
代理商： SL811S
SL811S/T
Document #: 38-08009 Rev. **
Page 13 of 27
Bit 5. USB Speed select.
‘
0
’
sets the USB Speed for Full Speed (12 MHz).
‘
1
’
sets the USB for Low Speed 1.5 MHz operation.
Bit 6.
‘
1
’
sets the USB Transceiver for low power operation. Suspend Mode (Low power operation) is entered when Bit 6 is set
=
‘
1
’
and Bit 0 (USB Enable) is set =
‘
0
’
.
5.4.2
The SL811S/T provides an Interrupt Request Output that is activated resulting from a number of conditions. The Interrupt Enable
Register allows the user to select activities that will generate the Interrupt Request. A separate Interrupt Status Register is
provided. It can be read in order to determine the condition that initiated the interrupt. (See Interrupt Status Register description).
When a bit is set to '1', the corresponding interrupt is enabled.
Interrupt Enable Register, Address [06h]
5.4.3
Contains USB Device Address after assignment by USB Host during configuration
. On power up or Reset, USB Address Register
is set to Address 00H. After USB configuration and address assignment, the device will recognize only USB transactions directed
to the address contained in the USB Address Register.
USB Address Register, Address [07h]
5.4.4
This Read/Write register serves as an Interrupt status register when it is read, and an Interrupt clear register when it is written.
To clear an interrupt bit, the register must be written with the appropriate bit set to '1'. Writing a '0' has no effect on the status.
Interrupt Status Register, Address [0Dh]
JK-Force State
USB Engine Reset
Function
0
0
Normal operating mode
0
1
Force SE0, D+ and D
–
are set low
1
0
Force K-State, D
–
set high, D+ set low
1
1
Force J-State, D+ set high, Dq
–
set low
Bit Position
Bit Name
Function
0
Endpoint 0 Done
Enable Endpoint 0 done Interrupt
1
Endpoint 1 Done
Enable Endpoint 1 done Interrupt
2
Endpoint 2 Done
Enable Endpoint 2 done Interrupt
3
Endpoint 3 Done
Enable Endpoint 3 done Interrupt
4
DMA Done
Enable DMA done Interrupt
5
SOF Received
Enable SOF Received Interrupt
6
USB Reset
Enable USB Reset received interrupt.
7
DMA Status
When
“
1
”
, indicates DMA transfer in progress; When
“
0
”
, indicates DMA
transfer is complete.*
Bit Position
Bit Name
Function
0
Endpoint 0 Done
Endpoint 0 done Interrupt
1
Endpoint 1 Done
Endpoint 1 done Interrupt
2
Endpoint 2 Done
Endpoint 2 done Interrupt
3
Endpoint 3 Done
Endpoint 3 done Interrupt
4
DMA Done
DMA done Interrupt
5
SOF Received
SOF Received Interrupt
6
USB Reset
USB Reset received interrupt.
7
DMA Status
When
“
1
”
, indicates DMA transfer in progress; When
“
0
”
, indicates DMA
transfer is complete. An interrupt is not generated when DMA is complete.
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