參數(shù)資料
型號(hào)： SL811S
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 總線控制器
英文描述： USB Dual Speed Slave Controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQCC28
封裝： PLASTIC, LCC-28
文件頁(yè)數(shù)： 10/27頁(yè)
文件大小： 181K
代理商： SL811S
SL811S/T
Document #: 38-08009 Rev. **
Page 10 of 27
Auto increment mode decreases the total time needed to transfer the block of data to or from the internal memory of the SL811S/T
controller, eliminating the need to set the address for each byte to be transferred. The advantage of this mode is that it reduces
the memory read or write cycles.
Please note when using some C Compilers, The Auto Increment mode may not work since some code implementations will
generate low level code causing read-modify-write cycles. This will result in address errors.
5.0
SL811S/T Registers
The registers in the SL811S/T are divided into two major groups. The first group contains Endpoint Registers that manage USB
control transactions and data flow. The second group contains the USB Registers that provide the control and status information
for all other operations.
5.1
Communication and data flow on the USB is implemented using endpoints. These uniquely identifiable entities are the terminals
of communication flow between a USB host and USB devices. Each USB device is composed of a collection of independently
operating endpoints. Each endpoint has a unique identifier, which is the Endpoint Number. For more information, see USB
Specification 1.1 section 5.3.1.
The SL811S/T supports 4 endpoints numbered 0
–
3. Endpoint 0 is the default pipe and is used to initialize and generically
manipulate the device to configure the logical device as the Default Control Pipe. It also provides access to the device's config-
uration information, allows USB status and control access, and supports control transfers.
Endpoints 1
–
3 support Bulk or Isochronous data transfers, and interrupts. Endpoint 3 is supported by DMA. Each endpoint has
two sets of registers
—
the 'a' set and the 'b' set. This allows overlapped operation where one set of parameters is being set up
and the other is transferring. Upon completion of a transfer to an endpoint, the 'next data set' bit indicates whether set 'a' or 'set
'b' will be in effect next. The 'armed' bit of the next data set will indicate whether the SL811S/T is ready for the next transfer without
interruption.
Endpoint Registers
5.2
Each endpoint set has a group of five registers that are mapped within the SL811S/T memory. The register sets have address
assignments as shown in the following table.
Endpoints 0
–
3 Register Addresses
For each endpoint set (starting at address Index = 0), the registers are mapped as shown in the following table:
Endpoint Register Set
Endpoint 0
–
a
Endpoint 0
–
b
Endpoint 1
–
a
Endpoint 1
–
b
Endpoint 2
–
a
Endpoint 2
–
b
Endpoint 3
–
a
Endpoint 3
–
b
Address (in Hex)
00 - 04
08 - 0C
10 - 14
18 - 1C
20 - 24
28 - 2C
30 - 34
38 - 3C
Endpoint Register Sets
(for Endpoint
n
starting at register position
Index=0
)
Index
Endpoint
n
Control
Index + 1
Endpoint
n
Base Address
Index + 2
Endpoint
n
Base Length
Index + 3
Endpoint
n
Packet Status
Index + 4
Endpoint
n
Transfer Count
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