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參數(shù)資料
| 型號(hào)： | SL811S |
| 廠(chǎng)商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 總線(xiàn)控制器 |
| 英文描述： | USB Dual Speed Slave Controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 12/27頁(yè) |
| 文件大?。?/td> | 181K |
| 代理商： | SL811S |
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SL811S/T
Document #: 38-08009 Rev. **
Page 12 of 27
5.4
The USB Control registers manage communication and data flow on the USB. Each USB device is composed of a collection of
independently operating endpoints. Each endpoint has a unique identifier, which is the Endpoint Number. For more details about
USB endpoints, please refer to the USB Specification 1.1, Section 5.3.1.
The control and status registers are mapped as follows:
USB Control Registers
5.4.1
The Control Register enables/disables USB transfers and DMA Operations with control bits.
Bit Position
Bit Name
Control Register, Address [05H]
Bit 0 should be set to
‘
1
’
to enable USB communication. The default is zero on power up.
Bit 1 is a DMA
enable
bit. DMA is initiated when DMA Count High is written.
Bit 2 sets the direction for DMA transfer.
Bits 3
–
4. The J-K force state control bits can be used to generate various USB bus conditions. Forcing K-state can be used for
Peripheral device remote wake-up, Resume and other modes. These two bits are set to zero on power up.
Register Name
Address (in Hex)
Control Register
05 h
Interrupt Enable Register
06 h
USB Address Register
07 h
Interrupt Status Register
0D h
Current Data Set Register
0E h
SOF Low Byte Register
15 h
SOF High Byte Register
16 h
DMA
Total Count Low Byte Register
35 h
DMA
Total Count High Byte Register
36 h
Function
0
USB Enable
Overall Enable for transfers. '1' enables, '0' disables.
1
DMA Enable
Enable DMA Operation when
‘
1
’
. Disable =
‘
0
’
.
2
DMA Dir
DMA transfer direction bit. Set
‘
1
’
for DMA read cycles from SL811S, Set
‘
0
’
for DMA
write cycles.
3
J-K0
J-K Force State Bit 0. [See Force State Table]
4
J-K1
J-K Force State Bit 1.
5
SPSEL
Speed Select.
‘
0
’
select FS.
‘
1
’
select LS
6
STBYD
XCVR Power control.
‘
1
’
sets XCVR to low power. Normally
‘
0
’
. Suspend mode is entered
if Bit 6 is set =
‘
1
’
and Bit 0 (USB Enable) is set =
‘
0
’
.
7
Reserved
Reserved bit - must be set to '0'.
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