
9
Revision 1/.ebruary 8, 2001
www.semtech.com
HIGH-PER.ORMANCE PRODUCTS
SK12430
ADVANCED
25
20
15
10
5
0
400
500
600
700
800
N = 2
N = 4
N = 8
RMS
Jitter
(ps)
Output Frequency (MHz)
Application Information (continued)
Generally the resistor/capacitor filter will be cheaper,
easier to implement and provide an adequate level
of supply filtering.
The SK12430 provides sub-nanosecond output edge
rates and thus a good power supply bypassing
scheme is a must.
Figure 6 shows
a representa-
tive board layout for the SK12430.
There exists
many different potential board layouts and the one
pictured below is but one. The important aspect of
the layout in Figure 6 is the low impedance connec-
tions between VCC and GND for the bypass capaci-
tors.
Combining good quality general purpose chip
capacitors with good PCB layout techniques will pro-
duce effective capacitor resonances at frquencies
adequate to supply the instantaneous switching cur-
rent for the 1240 outputs. It is imperative that low
inductance chip capacitors are used; it is equally
important that the board layout does not introduce
back all of the inductance saved by using the leadless
capacitors.
Thin interconnect traces between the
capacitor and the power plane should beavoided and
multiple large vias should be used to tie the capaci-
tors to the buried power planes.
Fat interconnect
and large vias will help to minimize layout induced
inductance and thus maximize the series resonant
point of the bypass capacitors.
the crystal is relatively small.
It is imperative that no
actively switching signals cross under the crystal as
crosstalk energy coupled to these lines could significantly
impact the jitter of the device. Special attention should
be paid to the layout of the crystal to ensure a stable,
jitter free interface between the crystal and the on-board
oscillator.
Although the SK12430 has several design features to
minimize the susceptibility to power supply noise (iso-
lated power and grounds and fully differential PLL), there
still may be applications in which overall performance is
being degraded due to system power supply noise. The
power supply filter and bypass schemes discussed in
this section should be adequate to eliminate power sup-
ply noise related problems in most designs.
Jitter Performance of the SK12430
The SK12430 exhibits long term and cycle-to-cycle jitter
which rivals that of SAW based oscillators.
This jitter
performance comes with the added flexibility one gets
with a synthesizer of a fixed frequency oscillator.
1
= VCC
= GND
= Via
R1
C3
C1
C2
Xtal
R1 = 10 15W
C1 = 0.01 F
C2 = 22 F
C3 = 0.1 F
Figure 6. PCB Board Layout for the SK12430
Note: The dotted lines circling the crystal oscillator
connection to the device. The oscillator is a series
resonant circuit and the voltage amplitude across
Figure 7. RMS Jitter versus VCO Frequency
Figure 7 illustrates the RMS jitter performance of the
SK12430 across its specified VCO frequency range. Note
that the jitter is a function of both the output frequency
as well as the VCO frequency
However, the VCO fre-
quency shows a much stronger dependence. The data
presented has not been compensated for trigger jitter
and this fact provides a measure of guardband to the
reported data.
The typical method of measuring the
jitter is to accumulate a large number of cycles, create a
histogram of the edge placements and record peak-to-
peak as well as standard deviations of the jitter. Care
must be taken that the measured edge is the edge im-
mediately following the trigger edge.