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參數(shù)資料
| 型號(hào)： | SK12430PJT |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大小： | 225K |
| 代理商： | SK12430PJT |
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6
Revision 1/.ebruary 8, 2001
www.semtech.com
HIGH-PER.ORMANCE PRODUCTS
SK12430
ADVANCED
M[8:0] and N[1:0] are normally specified once at a
power-up through the parallel interface, and then pos-
sibly again through the serial interface. This approach
allows the application to come up at one frequency
and then change or fine-tune the clock as the ability
to control the serial interface becomes available.
The TEST output provides visibility for one of the sev-
eral internal nodes as determined by the T[2:0] bits
in the serial configuration stream.
It is not
configurable through the parallel interface.
The T2
and TO control bits are preset to ‘000’ when P_LOAD*
is LOW so that the PECL FOUT outputs are as jitter-
free as possible. Any active signal on the TEXT out-
put pin will have detrimental affects on the jitter of
the PECL output pair. In normal operations, jitter speci-
fications are only guaranteed if the TEXT output is
static.
The serial configuration port can be used to
select one of the alternate functions for this pin.
Most of the signals available on the TEXT output pin
are useful only for performance verification of the
SK12430, itself. However, the PLL bypass mode may
be of interest at the board level for functional debug.
When T(2:0) is set to 110, the V is placed in PLL
bypass mode. In this mode the S_CLOCK input is fed
directly into the M and N dividers. The N divider drives
the FOUT differential pair and the M counter drives the
TEST output pin.
In this mode, the S_CLOCK input
could be used for low speed board level functional test
or debug. Bypassing the PLL and driving FOUT directly
gives the user more control on the test clocks sent
through the clock tree.
Figure 4 shows the functional
setup of the PLL bypass mode. Because the S_CLOCK
is a CMOS level, the input frequency is limited to
250MHz or less. This means the fastest the FOUT pin
can be toggled via the S_CLOCK is 250MHz as the
minimum divide ratio of the N counter is 1. Note that
the M counter ouptu on the TEST output will not be a
50% duty cycle due to the way the divider is imple-
mented.
First Bit
Last Bit
T1
T0
N1
N0
M6
M5
M4
M3
M2
M1
M0
T2
M, N
S_CLOCK
S_DATA
S_LOAD
P_LOAD*
M[6:0]
N[1:0]
Figure 3. Timing Diagram
2
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T0
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Application Information (continued)
Note: X = Don’t Care
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SK125 | 制造商:Thomas & Betts 功能描述: |
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| SK12516 | 制造商:Cooper Wiring Devices 功能描述: |
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