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參數(shù)資料
| 型號(hào)： | SK12430PJT |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 225K |
| 代理商： | SK12430PJT |
5
Revision 1/.ebruary 8, 2001
www.semtech.com
HIGH-PER.ORMANCE PRODUCTS
SK12430
ADVANCED
The serial interface centers on a fourteen bit shift
register.
The shift register shifts once per rising
edge of the S_CLOCK input. The serial input
S_DATA must meet setup and hold timing as speci-
fied in the AC Characteristics section of this docu-
ment.
The configuration latches will capture the
value of the shift register on the HIGH-to-LOW edge
of the S_LOAD input. See the programming section
for more information.
Programming the device amount to properly
configuring the internal dividers to produce the
desired frequency at the outputs. The output
frequency can by represented by this formula:
FOUT = (FXTAL
÷ 16) x M x 2 ÷N
(1)
Where F
XTAL
is the crystal frequency, M is the loop
divider modulus, and N is the output divider
modulus. Note that it is possible to select values
of M such that the PLL is unable to achieve loop
lock. To avoid this, always make sure that M is
selected to be 200
≤ M ≤ 400 for any input
reference.
Assuming that a 16MHz reference frequency is
used, the above equation reduces to:
FOUT = 2 X M
÷ N
Substituting the four values for N (1, 2, 4, 8)
yields:
Following this same procedure, a user can generate
any whole frequency desired between 50 and 800 MHz.
Note that for n> 2 fractional values of FOUT can be
realized. The size of the programmable frequency steps
(and thus the indicator of the fractional output fre-
quencies
achievable) will be equal to FXTAL
÷ 8 ÷ N. For input
reference frequencies other than 16MHz, the set of
appropriate equations can be deduced from equation
1. For computer applications, another useful frequency
base would be 16.666MHz reference, the following M
and N values would be used:
FOUT = 16.666
÷ 16 X M X 2 ÷ N = 1.04166 X M X 2 ÷ N
Let N = 4, M = 133.333
÷ 1.04166 X 2 = 256
The value for M falls within the constraints set for PLL
stability, therefore, N[1:0] = 01 and M[8:0] =
10000000. If the value for M fell outside of the valid
range, a different N value would be selected to try to
move M in the appropriate direction.
The M and N counters can be loaded either through a
parallel or serial interface.
The parallel interface is
controlled via the P_LOAD* signal such that a LOW to
HIGH transition will latch the information present on
the M[8:0] and N[1:0] inputs into the M and N counters.
When the P_LOAD* signal is LOW, the input latches
will be transparent and any changes on the M[8:0]
and N[1:0] inputs will affect the FOUT output pair. To
use the serial port, the S_CLOCK signal samples the
information on the S_DATA line and loads it into a 14
bit shift register.
Note that the P_LOAD* signal
must be HIGH for the serial load operation to function.
The test register is loaded with the first three bits, the
N register with the next two and the M register with
the final eight bits of the data stream on the S_DATA
input.
For each register, the most significant bit is
loaded first (T2, N1 and M8]. A pulse on the S_LOAD
pin after the shift register is fully loaded will transfer
the divide values into the counters. The HIGH to LOW
transition on the S_LOAD input will latch the new di-
vide values into the counters. Figure 3 illustrates the
timing diagram for both a parallel and a serial load of
the SK12430 synthesizer.
From these ranges, the user will establish the value
of N required, then the value of M can be calculated
based upon the appropriate equation above.
For ex-
ample, if an output frequency of 131 MHz was de-
sired, the following steps would be taken to identify
the appropriate M and N values. 131MHz falls within
the frequency range set by an N value of 4 so N [1:0]
= 01. For N = 4, FOUT - M
÷ 2 X FOUT. Therefore, M
= 131 X 2 = 262, so M[8:0] = 100000110.
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5
Programming Interface
Application Information
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