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參數(shù)資料
| 型號： | SK12430PJT |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 225K |
| 代理商： | SK12430PJT |
8
Revision 1/.ebruary 8, 2001
www.semtech.com
HIGH-PER.ORMANCE PRODUCTS
SK12430
ADVANCED
Application Information (continued)
current (the current sourced through the PLL_VCC pin)
is typically 15 mA (20mA maximum), assuming that a
minimum of 3.0V must be maintained on the PLL_VCC
pin, very little DC voltage drop can be tolerated when
a 3.3V VCC supply is used.
The resistor shown in
Figure 5 must have a resistance of 10-15
to meet
the voltage drop
criteria.
The RC filter pictured will
provide a broadband filter with approximately 100:1
attenuation for noise whose spectral content is above
20KHz.
As the noise frequency crosses the series
resonant point of an individual capacitor its overall
impedance begins to look inductive and thus increases
with increasing frequency. The parallel capacitor com-
bination show ensures that a low impedance path to
ground exists for rrequencies will above the bandwidth
of the PLL.
A higher level of attenuation can be achieved by re-
placing the resistor with an appropriate valued
inducto9r.
A 1000
H choke will show a significant
impedance at 10KHz frequencies and above. Because
of the current draw and the voltage that must be main-
tained on the PLL_VCC pin, a low voltage that must be
maintained on the PLL_VCC pin, a low DC resistance
inductor is required (less than 15
).
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5
Power Supply Filtering
The SK12430 is a mixed analog/digital product and
as such it exhibits some sensitivities that would not
necessarily be seen on a fully digital product. Ana-
log circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply
pins.
The SK12430 provides separate power sup-
plies for the digital circuitry (V
CC
) and the internal
PLL (PLL_VCC) of the device.
The purpose of this
design technique is to try and isolate the high switch-
ing noise digital outputs from the relatively sensi-
tive internal analog outputs from the relatively sen-
sitive internal analog phase-locked loop.
In a con-
trolled environment such as an evaluation board, this
level of isolation is sufficient.
However, in a digital
system environment where it is more difficult to mini-
mize noise on the power supplies a second level of
isolation may be required. The simplest from of iso-
lation is a power supply filter on the PLL_VCC
pin
for the SK12430.
Figure 5 illustrates a typical power supply filter
scheme. The SK12430 is most susceptible to noise
with spectral content in the 1KHz to 1MHz range.
Therefore, the filter should be designed to target
this range. The key parameter that needs to be met
in the final filter design is the DC voltage drop that
will be seen between the V
CC
supply and the PLL_VCC
pin of the SK12430. From the data sheet, the I
PLL_VCC
*see accompanying text for series versus parallel resonant discussion.
Table 1. Crystal Specifications
3.3V or 5.0V
RS= 10– 15W
SK12430
PLL_VCC
VCC
0.01 F
22 F
Figure 5. Power Supply Filter
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