參數(shù)資料
型號(hào): SI5327D-C-GMR
廠商: SILICON LABORATORIES
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 243 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC36
封裝: 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36
文件頁數(shù): 17/60頁
文件大?。?/td> 715K
代理商: SI5327D-C-GMR
Si5327
24
Preliminary Rev. 0.4
Reset value = 0100 0010
Reset value = 0000 0101
Register 2.
Bit
D7D6D5D4D3D2D1D0
Name
BWSEL_REG [3:0]
Type
R/W
R
RRR
Bit
Name
Function
7:4
BWSEL_REG
[3:0]
BWSEL_REG.
Selects nominal f3dB bandwidth for PLL. See DSPLLsim for settings. After BWSEL_REG
is written with a new value, an ICAL is required for the change to take effect.
3:0
Reserved
Register 3.
Bit
D7D6D5D4D3D2D1D0
Name
Reserved
DHOLD
SQ_ICAL
Type
R
R/W
R
RRR
Bit
Name
Function
7:6
Reserved
5
DHOLD
DHOLD.
Forces the part into digital hold. This bit overrides all other manual and automatic clock
selection controls.
0: Normal operation.
1: Force digital hold mode. Overrides all other settings and ignores the quality of all of the
input clocks.
4
SQ_ICAL
SQ_ICAL.
This bit determines if the output clocks will remain enabled or be squelched (disabled)
during an internal calibration. See Table 8 on page 20.
0: Output clocks enabled during ICAL.
1: Output clocks disabled during ICAL.
3:0
Reserved
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