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參數(shù)資料
| 型號(hào)： | SI5326C-C-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 11/72頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ANY-RATE MULTI/ATTEN 36-QFN |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 系列： | DSPLL® |
| 類型： | 時(shí)鐘放大器，振動(dòng)衰減器 |
| PLL： | 是 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CML，CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 346MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 1.71 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-VFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 36-QFN（6x6） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 628 (CN2011-ZH PDF) |
| 其它名稱： | 336-1746 336-1746-5 336-1746-ND |
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Si5326
Rev. 1.0
19
The Si5326 has two differential clock outputs. The
electrical format of each clock output is independently
programmable to support LVPECL, LVDS, CML, or
CMOS loads. If not required, the second clock output
can be powered down to minimize power consumption.
The phase difference between the selected input clock
and the output clocks is adjustable in 200 ps increments
for system skew control using the CLAT[7:0] register.
Fine phase adjustment is available and is set using the
FLAT
register bits. The nominal range and resolution of
the FLAT[14:0] skew adjustment word are: ±110 ps and
3 ps, respectively. In addition, the phase of one output
clock may be adjusted in relation to the phase of the
other output clock. The resolution varies from 800 ps to
2.2 ns depending on the PLL divider settings. See
Table 8 for instructions on ensuring output-to-output
alignment. The input to output skew is not specified.
The DSPLLsim software utility determines the phase
offset
resolution
for
a
given
input
clock/clock
multiplication ratio combination. For system-level
debugging, a bypass mode is available which drives the
output clock directly from the input clock, bypassing the
internal DSPLL. The device is powered by a single 1.8,
2.5, or 3.3 V supply.
4.1. External Reference
An external, high quality clock or a low-cost
114.285 MHz 3rd overtone crystal is used as part of a
fixed-frequency oscillator within the DSPLL. This
external reference is required for the device to perform
jitter attenuation. Silicon Laboratories recommends
using a high quality crystal. Specific recommendations
may be found in the Family Reference Manual.
In digital hold, the DSPLL remains locked and tracks the
external reference. Note that crystals can have
temperature sensitivities.
4.2. Further Documentation
Consult the Silicon Laboratories Si53xx Any Frequency
Precision Clock Family Reference Manual (FRM) for
detailed information about the Si5326 functions.
Additional design support is available from Silicon
Laboratories through your distributor.
Silicon Laboratories has developed a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing.
Table 8. CKOUT_ALWAYS_ON and SQ_ICAL Truth Table
CKOUT_ALWAYS_ON
SQ_ICAL
Results
0
CKOUT OFF until after the first ICAL
0
1
CKOUT OFF until after the first successful
ICAL (i.e., when LOL is low)
1
0
CKOUT always ON, including during an ICAL
1
CKOUT always ON, including during an ICAL.
Use these settings to preserve output-to-output
skew
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5326C-C-GMR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Precision Clk Xplier Jitter Attn 2In/Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5326C-C-GMR-TR | 制造商:Silicon Laboratories Inc 功能描述:SLLSI5326C-C-GMR-TR CLOCK (2 KHZ TO 346 |
| SI5326-VTSS-EVB | 制造商:Silicon Laboratories Inc 功能描述:Evaluation Board For Si5326 Sync-E Vitesse Timing Module 制造商:Silicon Laboratories Inc 功能描述:SI5326 EVALUATION BOARD - Trays |
| Si5327B-C-GM | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 LW LOOP BW AR CLK MULT/JITTER 2IN/OUT RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5327B-C-GMR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Lo Loop BW Clk Multi Jitter Attn 2In/Out RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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