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參數(shù)資料
| 型號： | SI5326C-C-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 10/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ANY-RATE MULTI/ATTEN 36-QFN |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 系列： | DSPLL® |
| 類型： | 時鐘放大器，振動衰減器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CML，CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 346MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 1.71 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 36-QFN（6x6） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 628 (CN2011-ZH PDF) |
| 其它名稱： | 336-1746 336-1746-5 336-1746-ND |
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Si5326
18
Rev. 1.0
4. Functional Description
Figure 6. Functional Block Diagram
The Si5326 is a jitter-attenuating precision clock
multiplier for applications requiring sub 1 ps jitter
performance. The Si5326 accepts two input clocks
ranging from 2 kHz to 710 MHz and generates two
output clocks ranging from 2 kHz to 945 MHz and select
frequencies to 1.4 GHz. The Si5326 can also use its
crystal oscillator as a clock source for frequency
synthesis. The device provides virtually any frequency
translation combination across this operating range.
Independent dividers are available for each input clock
and output clock, so the Si5326 can accept input clocks
at different frequencies and it can generate output
clocks at different frequencies. The Si5326 input clock
frequency
and
clock
multiplication
ratio
are
programmable through an I2C or SPI interface. Silicon
Laboratories offers a PC-based software utility,
DSPLLsim, that can be used to determine the optimum
PLL divider settings for a given input frequency/clock
multiplication ratio combination that minimizes phase
noise and power consumption. This utility can be
downloaded from http://www.silabs.com/timing.
The Si5326 is based on Silicon Laboratories' 3rd-
generation DSPLL technology, which provides any
frequency synthesis and jitter attenuation in a highly
integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The Si5326
PLL loop bandwidth is digitally programmable and
supports a range from 60 Hz to 8.4 kHz. The DSPLLsim
software utility can be used to calculate valid loop
bandwidth
settings
for
a
given
input
clock
frequency/clock multiplication ratio.
The Si5326 supports hitless switching between the two
synchronous input clocks in compliance with GR-253-
CORE that greatly minimizes the propagation of phase
transients to the clock outputs during an input clock
transition (maximum 200 ps phase change). Manual
and automatic revertive and non-revertive input clock
switching options are available. The Si5326 monitors
both input clocks for loss-of-signal (LOS) and provides a
LOS alarm (INT_C1B and C2B) when it detects missing
pulses on either input clock. The device monitors the
lock status of the PLL. The lock detect algorithm works
by continuously monitoring the phase of the input clock
in relation to the phase of the feedback clock. The
Si5326 also monitors frequency offset alarms (FOS),
which indicate if an input clock is within a specified
frequency band relative to the frequency of a reference
clock. Both Stratum 3/3E and SONET Minimum Clock
(SMC) FOS thresholds are supported.The Si5326
provides a digital hold capability that allows the device
to continue generation of a stable output clock when the
selected input reference is lost. During digital hold, the
DSPLL generates an output frequency based on a
historical average frequency that existed for a fixed
amount of time before the error event occurred,
eliminating the effects of phase and frequency
transients that may occur immediately preceding digital
hold.
DSPLL
Loss of Signal/
Frequency Offset
Xtal or Refclock
CKOUT2
CKIN1
CKOUT1
CKIN2
÷ N31
÷ N2
÷ N1_LS
÷ N2_LS
Skew Control
Signal Detect
Device Interrupt
VDD (1.8, 2.5, or 3.3 V)
GND
÷ N32
Loss of Lock
Clock Select
I2C/SPI Port
Control
Rate Select
÷ N1_HS
Xtal/Refclock
Hitless Switching
Mux
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5326C-C-GMR | 功能描述:時鐘合成器/抖動清除器 Precision Clk Xplier Jitter Attn 2In/Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5326C-C-GMR-TR | 制造商:Silicon Laboratories Inc 功能描述:SLLSI5326C-C-GMR-TR CLOCK (2 KHZ TO 346 |
| SI5326-VTSS-EVB | 制造商:Silicon Laboratories Inc 功能描述:Evaluation Board For Si5326 Sync-E Vitesse Timing Module 制造商:Silicon Laboratories Inc 功能描述:SI5326 EVALUATION BOARD - Trays |
| Si5327B-C-GM | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 LW LOOP BW AR CLK MULT/JITTER 2IN/OUT RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5327B-C-GMR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Lo Loop BW Clk Multi Jitter Attn 2In/Out RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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